Abstract: Aspects of a storage device are provided for handling GBBs with defects between global interconnects and local word lines. The storage device includes a plurality of blocks each including a plurality of word lines, a plurality of interconnects within an interconnect set and between multiple ones of the blocks, volatile memory, and a controller. The controller determines a logical address pattern associated with the multiple ones of the blocks respectively including a program failure, determines whether the logical address pattern is associated with the interconnect set for the multiple ones of the blocks, determines a common word line associated with the program failures in the multiple ones of the blocks, un-marks these blocks as GBBs, and refrains from programming the common word line during respective program operations in the multiple ones of the blocks. Thus, blocks may be reclaimed, defective word line(s) isolated, and likelihood of read-only modes reduced.

Abstract: Technology is disclosed herein for checking data integrity in a non-volatile storage system. The storage system may operate in a first mode in which a data integrity check is performed in closed blocks until more than an allowed number of word lines fail the data integrity check. After a closed block has more than the allowed number of the word lines fail the data integrity check, then the storage system may operate in a second mode in which a data integrity check is performed in open blocks. The allowed number of word lines may be equal to the number of word lines that can be recovered by XOR data in the event data is uncorrectable by an ECC engine. The data integrity check of a target word line in an open block may be performed after programming a word line adjacent to the target word line in the open block.

Abstract: Technology is disclosed herein for checking data integrity in a non-volatile storage system. The storage system may operate in a first mode in which a data integrity check is performed in closed blocks until more than an allowed number of word lines fail the data integrity check. After a closed block has more than the allowed number of the word lines fail the data integrity check, then the storage system may operate in a second mode in which a data integrity check is performed in open blocks. The allowed number of word lines may be equal to the number of word lines that can be recovered by XOR data in the event data is uncorrectable by an ECC engine. The data integrity check of a target word line in an open block may be performed after programming a word line adjacent to the target word line in the open block.

Abstract: Technology is disclosed herein for memory health monitoring and mitigation based on decoding statistics. Decoding a frame results in a decoding metric (syndrome weight, fail bit count) for that frame. The system tracks a statistic for different sets of frames. The statistic for a set is based on the decoding metrics for that set. The frames may be assigned to sets based on read reference voltages used to read frames or the physical location of the memory cells that store the frames. Memory health mitigation may be performed based on the decoding statistics. One example mitigation is to modify the read reference voltages for the set. Another example mitigation is to trigger reading at soft bit reference levels for a block. Another example mitigation is to trigger direct look ahead reading for a block. Still another example mitigation is to add a block to list of candidates for data refresh.

Abstract: Aspects of a storage device are provided for handling GBBs with defects between global interconnects and local word lines. The storage device includes a plurality of blocks each including a plurality of word lines, a plurality of interconnects within an interconnect set and between multiple ones of the blocks, volatile memory, and a controller. The controller determines a logical address pattern associated with the multiple ones of the blocks respectively including a program failure, determines whether the logical address pattern is associated with the interconnect set for the multiple ones of the blocks, determines a common word line associated with the program failures in the multiple ones of the blocks, un-marks these blocks as GBBs, and refrains from programming the common word line during respective program operations in the multiple ones of the blocks. Thus, blocks may be reclaimed, defective word line(s) isolated, and likelihood of read-only modes reduced.

Abstract: A non-volatile storage system comprises memory cells arranged in groups of memory cells that include programmable select gates and one or more control circuits in communication with the memory cells. The one or more control circuits configured to identify a select gate that needs to be programmed and program the select gate identified to be programmed if a temperature at the non-volatile memory cells is greater than a minimum temperature and defer programming of the select gate identified to be programmed until the temperature at the non-volatile memory cells is greater than the minimum temperature. In some embodiments, the one or more control circuits are configured to perform dummy memory operations on the plurality of non-volatile memory cells to raise the temperature of the non-volatile memory cells in response to determining that the temperature at the non-volatile memory cells is not high enough.

Abstract: A non-volatile storage system comprises memory cells arranged in groups of memory cells that include programmable select gates and one or more control circuits in communication with the memory cells. The one or more control circuits configured to identify a select gate that needs to be programmed and program the select gate identified to be programmed if a temperature at the non-volatile memory cells is greater than a minimum temperature and defer programming of the select gate identified to be programmed until the temperature at the non-volatile memory cells is greater than the minimum temperature. In some embodiments, the one or more control circuits are configured to perform dummy memory operations on the plurality of non-volatile memory cells to raise the temperature of the non-volatile memory cells in response to determining that the temperature at the non-volatile memory cells is not high enough.