Patents by Inventor Mahiro Hikita
Mahiro Hikita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7233613Abstract: The present invention provides a synchronization establishing device and method for establishing synchronization at a high speed in a receiver. This synchronization establishing device includes a storage unit that accumulates reception data, and a matched filter that reads out the reception data accumulated in the storage unit in parallel and determines a correlation value by obtaining correlation between a common code and the reception data in parallel.Type: GrantFiled: February 21, 2001Date of Patent: June 19, 2007Assignee: Fujitsu LimitedInventors: Shoji Taniguchi, Koichi Kuroiwa, Masami Kanasugi, Mahiro Hikita
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Patent number: 7085252Abstract: A power threshold value (12) is set to be compared with a correlation power value detected by a correlator (2) and a power conversion section (4). As a result of comparison by a comparator (13), only the correlation power values that exceed the threshold value (12) are stored in a power value memory (14), and unnecessary correlation values at noise levels are not stored in the memory (14) so that the number of power values stored can be decreased. With this construction, the necessary memory capacity can be decreased, and the process of searching for the maximum value from the correlation power values stored in the memory (14) can be performed at a higher speed.Type: GrantFiled: March 31, 2000Date of Patent: August 1, 2006Assignee: Fujitsu LimitedInventors: Koichi Kuroiwa, Masami Kanasugi, Mahiro Hikita, Shoji Taniguchi
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Publication number: 20060150067Abstract: An error detector at a receiver comprises a feedback shift register. A shift direction in the feedback shift register is opposite to a shift direction at a transmitter in generating a transmission bit string by using a specified generator polynomial. A reception bit string is inputted to the feedback shift register in reverse order to the transmission bit string was generated at the transmitter so that errors in the reception bit string is detected by obtaining the remainder. Another error detector at a receiver comprises first and second feedback shift registers. Respective shift directions in the first and second feedback shift registers are the same as and opposite to a shift direction at a transmitter in generating a transmission bit string.Type: ApplicationFiled: February 10, 2006Publication date: July 6, 2006Inventors: Masami Kanasugi, Shoji Taniguchi, Koichi Kuroiwa, Mahiro Hikita
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Patent number: 7051059Abstract: When changing the number of oversamples is performed, tap factors selected by selectors, which respectively correspond to holding parts in a shift register, are changed back to a predetermined number of tap factors used before the changing of the number of oversamples, in which every time input data is accepted, the changes of the tap factors are performed in sequence, starting from the selector corresponding to the holding part at the input side. This allows the individual selectors to select proper tap factors according to the input data after the changing of the number of oversamples. As a result, the continuity of the output data is maintained even before and after the number of oversamples is changed.Type: GrantFiled: March 27, 2001Date of Patent: May 23, 2006Assignee: Fujitsu LimitedInventors: Masami Kanasugi, Shoji Taniguchi, Koichi Kuroiwa, Mahiro Hikita
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Patent number: 7035318Abstract: A receiving unit for receiving a CDMA system signal having a plurality of multipath components is intended to reduce the size. A receiving section receives a CDMA system signal. A storage section stores the signal received by the receiving section. A demodulation section demodulates each of multipath components included in the received signal stored in the storage section with a despreading code. A control section controls for demodulating a plurality of the multipath components by causing the demodulation section to perform a time division multiplex process. A Rake combining section performs the maximal ratio combining of output from the demodulation section to generate a demodulated signal.Type: GrantFiled: March 26, 2002Date of Patent: April 25, 2006Assignee: Fujitsu LimitedInventors: Shoji Taniguchi, Koichi Kuroiwa, Masami Kanasugi, Yoshikazu Yamada, Mahiro Hikita
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Patent number: 7032161Abstract: An error detector at a receiver comprises a feedback shift register. A shift direction in the feedback shift register is opposite to a shift direction at a transmitter in generating a transmission bit string by using a specified generator polynomial. A reception bit string is inputted to the feedback shift register in reverse order to the transmission bit string was generated at the transmitter so that errors in the reception bit string is detected by obtaining the remainder. Another error detector at a receiver comprises first and second feedback shift registers. Respective shift directions in the first and second feedback shift registers are the same as and opposite to a shift direction at a transmitter in generating a transmission bit string.Type: GrantFiled: August 20, 2002Date of Patent: April 18, 2006Assignee: Fujitsu LimitedInventors: Masami Kanasugi, Shoji Taniguchi, Koichi Kuroiwa, Mahiro Hikita
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Patent number: 7028062Abstract: The FIR filter separately receives input data consisting of transmitting information and composed of bit strings, and additional data which is added in order to transmit the input data. The input data is operated with the additional data. A difference between the additional data corresponding to previous data (for instance, most recent data) among the input data and the additional data corresponding present data is obtained, and the difference and the previous data are operated. Then, the operation results are added and the resultant is outputted as a filter response. The input data and the additional data are separately received to be operated so that the circuit scale of the filter is reduced. Therefore, a chip of the semiconductor integrated circuit can be downsized and thereby cost reduction in the communication system can be realized.Type: GrantFiled: August 13, 2001Date of Patent: April 11, 2006Assignee: Fujitsu LimitedInventors: Masami Kanasugi, Shoji Taniguchi, Koichi Kuroiwa, Mahiro Hikita
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Patent number: 6678315Abstract: A code phase setting method in a PN coder which includes a shift register is provided. According to the method, an initial value is set in the shift register and a direction is selected among two directions in which direction a value in the shift register is shifted. Then, a code phase is set by shifting the initial value in the direction a necessary number of times.Type: GrantFiled: November 23, 1999Date of Patent: January 13, 2004Assignee: Fujitsu LimitedInventors: Mahiro Hikita, Shoji Taniguchi, Koichi Kuroiwa, Masami Kanasugi
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Patent number: 6647405Abstract: An adding circuit which receives addend data and augend data, each of which consists of a plurality of bits, and sums the addend and augend data, comprises: a plurality of addition blocks, each of which is used to add a predetermined number of bits of the addend data to a like number of bits of the augend data, and for outputting both the result obtained by adding the predetermined number of bits and a carry-out signal, wherein, when a carry-out occurs for one of the addition blocks, in accordance with a carry-out signal from a lower rank and a set comprising the addend data and the augend data, the pertinent addition block responds to the pertinent carry-out, and wherein, when a carry-out does not occur for the addition block in accordance with the set comprising the addend data and the augend data, the pertinent addition block responds to the carry-out and generates a block addition end signal which indicates that the addition performed by the addition block has been completed.Type: GrantFiled: March 9, 2000Date of Patent: November 11, 2003Assignee: Fujitsu LimitedInventors: Koichi Kuroiwa, Shoji Taniguchi, Masami Kanasugi, Mahiro Hikita
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Patent number: 6639954Abstract: A mobile communication terminal which receives convolutionally encoded data that is convolutionally encoded information of a speech channel transmitted from a base station and detects a transmission bit rate selected at the base station by decoding the data. The mobile communication terminal comprises a rate estimation unit which estimates the transmission bit rate selected at the base station and outputs an estimated transmission bit rate, a decoding unit which decodes the convolutionally encoded data transmitted from the base station and outputs decoded data and predetermined types of results of decoding, a convolutional re-encoding unit which convolutionally re-encodes the decoded data and outputs re-encoded data, and a rate detection unit which detects whether the estimated transmission bit rate is correct or not based on the decoded data and the predetermined types of results of decoding.Type: GrantFiled: May 26, 1999Date of Patent: October 28, 2003Assignee: Fujitsu LimitedInventors: Koichi Kuroiwa, Mahiro Hikita
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Publication number: 20030095613Abstract: A mobile communication terminal which receives convolutionally encoded data that is convolutionally encoded information of a speech channel transmitted from a base station and detects a transmission bit rate selected at the base station by decoding the data. The mobile communication terminal comprises a rate estimation unit which estimates the transmission bit rate selected at the base station and outputs an estimated transmission bit rate, a decoding unit which decodes the convolutionally encoded data transmitted from the base station and outputs decoded data and predetermined types of results of decoding, a convolutional re-encoding unit which convolutionally re-encodes the decoded data and outputs re-encoded data, and a rate detection unit which detects whether the estimated transmission bit rate is correct or not based on the decoded data and the predetermined types of results of decoding.Type: ApplicationFiled: May 26, 1999Publication date: May 22, 2003Inventors: KOICHI KUROIWA, MAHIRO HIKITA
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Publication number: 20030067965Abstract: A receiving unit for receiving a CDMA system signal having a plurality of multipath components is intended to reduce the size. A receiving section receives a CDMA system signal. A storage section stores the signal received by the receiving section. A demodulation section demodulates each of multipath components included in the received signal stored in the storage section with a despreading code. A control section controls for demodulating a plurality of the multipath components by causing the demodulation section to perform a time division multiplex process. A Rake combining section performs the maximal ratio combining of output from the demodulation section to generate a demodulated signal.Type: ApplicationFiled: March 26, 2002Publication date: April 10, 2003Applicant: FUJITSU LIMITED of KAWASAKI, JAPANInventors: Shoji Taniguchi, Koichi Kuroiwa, Masami Kanasugi, Yoshikazu Yamada, Mahiro Hikita
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Publication number: 20030046636Abstract: An error detector at a receiver comprises a feedback shift register. A shift direction in the feedback shift register is opposite to a shift direction at a transmitter in generating a transmission bit string by using a specified generator polynomial. A reception bit string is inputted to the feedback shift register in reverse order to the transmission bit string was generated at the transmitter so that errors in the reception bit string is detected by obtaining the remainder. Another error detector at a receiver comprises first and second feedback shift registers. Respective shift directions in the first and second feedback shift registers are the same as and opposite to a shift direction at a transmitter in generating a transmission bit string.Type: ApplicationFiled: August 20, 2002Publication date: March 6, 2003Applicant: Fujitsu LimitedInventors: Masami Kanasugi, Shoji Taniguchi, Koichi Kuroiwa, Mahiro Hikita
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Patent number: 6493844Abstract: An error detector at a receiver comprises a feedback shift register. A shift direction in the feedback shift register is opposite to a shift direction at a transmitter in generating a transmission bit string by using a specified generator polynomial. A reception bit string is inputted to the feedback shift register in reverse order to the transmission bit string generated at the transmitter so that errors in the reception bit string are detected by obtaining the remainder. Another error detector at a receiver comprises first and second feedback shift registers. Respective shift directions in the first and second feedback shift registers are the same as and opposite to a shift direction at a transmitter in generating a transmission bit string.Type: GrantFiled: May 14, 1999Date of Patent: December 10, 2002Assignee: Fujitsu LimitedInventors: Masami Kanasugi, Shoji Taniguchi, Koichi Kuroiwa, Mahiro Hikita
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Publication number: 20020023115Abstract: When changing the number of oversamples is performed, tap factors selected by selectors, which respectively correspond to holding parts in a shift register, are changed back to a predetermined number of tap factors used before the changing of the number of oversamples, in which every time input data is accepted, the changes of the tap factors are performed in sequence, starting from the selector corresponding to the holding part at the input side. This allows the individual selectors to select proper tap factors according to the input data after the changing of the number of oversamples. As a result, the continuity of the output data is maintained even before and after the number of oversamples is changed.Type: ApplicationFiled: March 27, 2001Publication date: February 21, 2002Inventors: Masami Kanasugi, Shoji Taniguchi, Koichi Kuroiwa, Mahiro Hikita
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Publication number: 20020002572Abstract: The FIR filter separately receives input data consisting of transmitting information and composed of bit strings, and additional data which is added in order to transmit the input data. The input data is operated with the additional data. A difference between the additional data corresponding to previous data (for instance, most recent data) among the input data and the additional data corresponding present data is obtained, and the difference and the previous data are operated. Then, the operation results are added and the resultant is outputted as a filter response. The input data and the additional data are separately received to be operated so that the circuit scale of the filter is reduced. Therefore, a chip of the semiconductor integrated circuit can be downsized and thereby cost reduction in the communication system can be realized.Type: ApplicationFiled: August 13, 2001Publication date: January 3, 2002Inventors: Masami Kanasugi, Shoji Taniguchi, Koichi Kuroiwa, Mahiro Hikita
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Publication number: 20010046257Abstract: The present invention provides a synchronization establishing device and method for establishing synchronization at a high speed in a receiver. This synchronization establishing device includes a storage unit that accumulates reception data, and a matched filter that reads out the reception data accumulated in the storage unit in parallel and determines a correlation value by obtaining correlation between a common code and the reception data in parallel. The present invention also provides the receiver.Type: ApplicationFiled: February 21, 2001Publication date: November 29, 2001Inventors: Shoji Taniguchi, Koichi Kuroiwa, Masami Kanasugi, Mahiro Hikita