Patents by Inventor Mahiro Tsujino

Mahiro Tsujino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9640452
    Abstract: An electronic component housing package has an input/output member that is bonded to a hole part of a frame body via a brazing material. This input/output member has a top surface that is bonded to first side wall parts and a second side wall part inside the first side wall parts, and the top surface is provided with a narrow part having a narrow width at a portion that is bonded to the first side wall part. When the input/output member is bonded, the flow of the brazing material on the top surface can be controlled by the narrow part.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: May 2, 2017
    Assignee: KYOCERA CORPORATION
    Inventors: Mahiro Tsujino, Daisuke Sakumoto
  • Patent number: 9491873
    Abstract: An element housing package includes a base body having a rectangular shape, having a mounting region for mounting a semiconductor element, a frame body disposed so as to surround the mounting region, a connection conductor disposed from the upper surface to a lower surface of the base body, a circuit conductor disposed on the lower surface of the base body, one end of the circuit conductor being electrically connected to the connection conductor and an other end of the circuit conductor being drawn out laterally from a first side surface of the base body, and a metal plate bonded to the lower surface of the base body, having an attachment region and a ground conductor region. The metal plate has an outer peripheral region which is drawn out laterally from the base body, from the ground conductor region to the attachment region along an outer periphery of the base body.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: November 8, 2016
    Assignee: Kyocera Corporation
    Inventor: Mahiro Tsujino
  • Patent number: 9443777
    Abstract: A semiconductor element housing package includes a rectangular ceramic package having a recess section on an upper surface thereof or a penetration section from the upper surface to a lower surface thereof, and a heat radiation plate attached to the lower surface of the ceramic package, extending from one side toward the other side of the lower surface up to a region in which the heat radiation plate overlays the recess section or the penetration section, which plate has a width on a side of the other side which is narrower than that on a side of one side. The package includes a plurality of first lead pins disposed on the lower surface of the ceramic package along the other side, and a pair of second lead pins disposed on the lower surface of the ceramic package on both sides of a narrow portion of the heat radiation plate.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: September 13, 2016
    Assignee: KYOCERA CORPORATION
    Inventors: Mahiro Tsujino, Toshihiko Kitamura
  • Patent number: 9408307
    Abstract: A device housing package includes a substrate in a form of a rectangle, having a mounting region of a device at an upper surface thereof; a frame body disposed on the substrate so as to extend along an outer periphery of the mounting region, the frame body having a cutout formed at a part thereof; and an input-output terminal disposed in the cutout. The input-output terminal includes a first insulating layer, a second insulating layer overlaid on the first insulating layer, and a third insulating layer overlaid on the second insulating layer. First terminals set at a predetermined potential are disposed on an upper surface of the first insulating layer. Second terminals set at a predetermined potential are disposed on a lower surface of the first insulating layer. Third terminals through which AC signals flow are disposed on an upper surface of the second insulating layer.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: August 2, 2016
    Assignee: Kyocera Corporation
    Inventors: Mahiro Tsujino, Eiichi Katayama, Emi Mukai, Atsushi Ogasawara
  • Patent number: 9386687
    Abstract: While it is necessary for an electronic component housing package to be provided with numerous wiring conductors, phase differences of signals caused by differences in signal transmission distance among the wiring conductors, is a problem. An electronic component housing package based on one embodiment includes a substrate having a dielectric region and an electronic component placement region, a frame body surrounding the dielectric region and the placement region, and wiring conductors disposed on the dielectric region of the substrate. The wiring conductors have a first wiring conductor and a second wiring conductor which is longer in signal transmission distance than the first wiring conductor, which are disposed so as to extend from a location immediately below the frame body to the dielectric region. The frame body made of a dielectric material has a projection protruding from its inner periphery, which covers at least part of the first wiring conductor.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: July 5, 2016
    Assignee: KYOCERA CORPORATION
    Inventors: Mahiro Tsujino, Yoshiki Kawazu
  • Publication number: 20160104650
    Abstract: An electronic component housing package has an input/output member that is bonded to a hole part of a frame body via a brazing material. This input/output member has a top surface that is bonded to first side wall parts and a second side wall part inside the first side wall parts, and the top surface is provided with a narrow part having a narrow width at a portion that is bonded to the first side wall part. When the input/output member is bonded, the flow of the brazing material on the top surface can be controlled by the narrow part.
    Type: Application
    Filed: September 25, 2014
    Publication date: April 14, 2016
    Applicant: KYOCERA CORPORATION
    Inventors: Mahiro TSUJINO, Daisuke SAKUMOTO
  • Patent number: 9078347
    Abstract: An electronic component housing unit includes: a substrate including a mounting region on which an electronic component is mounted; a connection conductor extending from a top face to a bottom face of the substrate, the connection conductor being electrically connected to the electronic component; a wiring conductor disposed on the bottom face of the substrate, one end of the wiring conductor being electrically connected to the connection conductor, another end of the wiring conductor being drawn out from a side face of the substrate; and a ground conductor disposed on the bottom face of the substrate, the ground conductor forming a coplanar line along with the wiring conductor. A bottom face of the wiring conductor is located above a bottom face of the ground conductor.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: July 7, 2015
    Assignee: KYOCERA Corporation
    Inventor: Mahiro Tsujino
  • Publication number: 20150130043
    Abstract: A semiconductor element housing package includes a rectangular ceramic package having a recess section on an upper surface thereof or a penetration section from the upper surface to a lower surface thereof, and a heat radiation plate attached to the lower surface of the ceramic package, extending from one side toward the other side of the lower surface up to a region in which the heat radiation plate overlays the recess section or the penetration section, which plate has a width on a side of the other side which is narrower than that on a side of one side. The package includes a plurality of first lead pins disposed on the lower surface of the ceramic package along the other side, and a pair of second lead pins disposed on the lower surface of the ceramic package on both sides of a narrow portion of the heat radiation plate.
    Type: Application
    Filed: May 16, 2013
    Publication date: May 14, 2015
    Applicant: KYOCERA Corporation
    Inventors: Mahiro Tsujino, Toshihiko Kitamura
  • Patent number: 8952518
    Abstract: A semiconductor device housing package includes a base body having, on its upper surface, a mounting region of a semiconductor device; a frame body having a frame-like portion disposed on the upper surface of the base body, surrounding the mounting region, and an opening penetrating through from an inner side of the frame-like portion to an outer side thereof; a flat plate-like insulating member disposed in the opening, extending from an interior of the frame body to an exterior thereof; wiring conductors disposed on an upper surface of the insulating member, extending from the interior of the frame body to the exterior thereof; and a metallic film disposed on a part of the upper surface of the insulating member, the metallic film lying outside the frame body surrounding the wiring conductors.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: February 10, 2015
    Assignee: Kyocera Corporation
    Inventors: Mahiro Tsujino, Manabu Miyahara
  • Publication number: 20150016074
    Abstract: A device housing package includes a substrate in a form of a rectangle, having a mounting region of a device at an upper surface thereof; a frame body disposed on the substrate so as to extend along an outer periphery of the mounting region, the frame body having a cutout formed at a part thereof; and an input-output terminal disposed in the cutout. The input-output terminal includes a first insulating layer, a second insulating layer overlaid on the first insulating layer, and a third insulating layer overlaid on the second insulating layer. First terminals set at a predetermined potential are disposed on an upper surface of the first insulating layer. Second terminals set at a predetermined potential are disposed on a lower surface of the first insulating layer. Third terminals through which AC signals flow are disposed on an upper surface of the second insulating layer.
    Type: Application
    Filed: March 5, 2013
    Publication date: January 15, 2015
    Applicant: KYOCERA Corporation
    Inventors: Mahiro Tsujino, Eiichi Katayama, Emi Mukai, Atsushi Ogasawara
  • Publication number: 20140345929
    Abstract: While it is necessary for an electronic component housing package to be provided with numerous wiring conductors, phase differences of signals caused by differences in signal transmission distance among the wiring conductors, is a problem. An electronic component housing package based on one embodiment includes a substrate having a dielectric region and an electronic component placement region, a frame body surrounding the dielectric region and the placement region, and wiring conductors disposed on the dielectric region of the substrate. The wiring conductors have a first wiring conductor and a second wiring conductor which is longer in signal transmission distance than the first wiring conductor, which are disposed so as to extend from a location immediately below the frame body to the dielectric region. The frame body made of a dielectric material has a projection protruding from its inner periphery, which covers at least part of the first wiring conductor.
    Type: Application
    Filed: December 20, 2012
    Publication date: November 27, 2014
    Inventors: Mahiro Tsujino, Yoshiki Kawazu
  • Patent number: 8653649
    Abstract: A device housing package includes a substrate having a device mounting region; a frame body having a through hole formed in part thereof, the frame body being disposed on the substrate so as to lie along a periphery of the device mounting region; and an input-output terminal disposed in the through hole, having a first dielectric layer; a signal line formed on the first dielectric layer; a first ground layer formed on a lower face of the first dielectric layer; a second dielectric layer formed on the signal line so as to overlap the frame body; a second ground layer formed on an upper face of the second dielectric layer; and a metal layer disposed within the second dielectric layer The metal layer is formed to extend from the second dielectric layer to the first dielectric layer, being separated from the signal line.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: February 18, 2014
    Assignee: Kyocera Corporation
    Inventors: Mahiro Tsujino, Mamoru Kinoshita, Kiyoshige Miyawaki
  • Publication number: 20140008780
    Abstract: A semiconductor device housing package includes a base body having, on its upper surface, a mounting region of a semiconductor device; a frame body having a frame-like portion disposed on the upper surface of the base body, surrounding the mounting region, and an opening penetrating through from an inner side of the frame-like portion to an outer side thereof; a flat plate-like insulating member disposed in the opening, extending from an interior of the frame body to an exterior thereof; wiring conductors disposed on an upper surface of the insulating member, extending from the interior of the frame body to the exterior thereof; and a metallic film disposed on a part of the upper surface of the insulating member, the metallic film lying outside the frame body surrounding the wiring conductors.
    Type: Application
    Filed: July 20, 2012
    Publication date: January 9, 2014
    Inventors: Mahiro Tsujino, Manabu Miyahara
  • Publication number: 20130322036
    Abstract: An element housing package includes a base body having a rectangular shape, having a mounting region for mounting a semiconductor element, a frame body disposed so as to surround the mounting region, a connection conductor disposed from the upper surface to a lower surface of the base body, a circuit conductor disposed on the lower surface of the base body, one end of the circuit conductor being electrically connected to the connection conductor and an other end of the circuit conductor being drawn out laterally from a first side surface of the base body, and a metal plate bonded to the lower surface of the base body, having an attachment region and a ground conductor region. The metal plate has an outer peripheral region which is drawn out laterally from the base body, from the ground conductor region to the attachment region along an outer periphery of the base body.
    Type: Application
    Filed: May 29, 2012
    Publication date: December 5, 2013
    Inventor: Mahiro Tsujino
  • Publication number: 20130128467
    Abstract: An electronic component housing unit includes: a substrate including a mounting region on which an electronic component is mounted; a connection conductor extending from a top face to a bottom face of the substrate, the connection conductor being electrically connected to the electronic component; a wiring conductor disposed on the bottom face of the substrate, one end of the wiring conductor being electrically connected to the connection conductor, another end of the wiring conductor being drawn out from a side face of the substrate; and a ground conductor disposed on the bottom face of the substrate, the ground conductor forming a coplanar line along with the wiring conductor. A bottom face of the wiring conductor is located above a bottom face of the ground conductor.
    Type: Application
    Filed: July 29, 2011
    Publication date: May 23, 2013
    Applicant: KYOCERA CORPORATION
    Inventor: Mahiro Tsujino
  • Patent number: 8344259
    Abstract: A connection terminal has, on an upper surface of a first dielectric layer, a first line conductor and a first grounding line conductor provided adjacent to both sides of the first line conductor, and has, on an upper surface of a third dielectric layer, a third line conductor and a third grounding line conductor provided adjacent to both sides of the third line conductor. These conductors are connected to a second line conductor and a second grounding line conductor provided adjacent to both sides of the second line conductor, respectively, the second line conductor and the second grounding line conductor being provided on an upper surface of a second dielectric layer. It is possible to obtain the connection terminal having a small size and capable of complying with a high-frequency signal.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: January 1, 2013
    Assignee: Kyocera Corporation
    Inventor: Mahiro Tsujino
  • Publication number: 20120147539
    Abstract: A device housing package includes a substrate having a device mounting region; a frame body having a through hole formed in part thereof, the frame body being disposed on the substrate so as to lie along a periphery of the device mounting region; an input-output terminal disposed in the through hole, having a first dielectric layer; a signal line formed on the first dielectric layer; a first ground layer formed on a lower face of the first dielectric layer; a second dielectric layer formed on the signal line so as to overlap the frame body; a second ground layer formed on an upper face of the second dielectric layer; and a metal layer disposed within the second dielectric layer The metal layer is formed to extend from the second dielectric layer to the first dielectric layer, being separated from the signal line.
    Type: Application
    Filed: September 24, 2010
    Publication date: June 14, 2012
    Applicant: KYOCERA CORPORATION
    Inventors: Mahiro Tsujino, Mamoru Kinoshita, Kiyoshige Miyawaki
  • Publication number: 20110048796
    Abstract: A connector which can be made compact is provided. A package and an electronic device which can be made compact by using the connector are also provided.
    Type: Application
    Filed: January 30, 2009
    Publication date: March 3, 2011
    Applicant: KYOCERA CORPORATION
    Inventor: Mahiro Tsujino
  • Publication number: 20100252313
    Abstract: A connection terminal has, on an upper surface of a first dielectric layer, a first line conductor and a first grounding line conductor provided adjacent to both sides of the first line conductor, and has, on an upper surface of a third dielectric layer, a third line conductor and a third grounding line conductor provided adjacent to both sides of the third line conductor. These conductors are connected to a second line conductor and a second grounding line conductor provided adjacent to both sides of the second line conductor, respectively, the second line conductor and the second grounding line conductor being provided on an upper surface of a second dielectric layer. It is possible to obtain the connection terminal having a small size and capable of complying with a high-frequency signal.
    Type: Application
    Filed: October 30, 2008
    Publication date: October 7, 2010
    Applicant: KYOCERA CORPORATION
    Inventor: Mahiro Tsujino