Patents by Inventor Mahito Sawada

Mahito Sawada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6579787
    Abstract: A plurality of metal wire layers consisting of a first metal wire layer and a second metal wire layer are formed on a semiconductor substrate. A fluorinated silicate glass film serving as an interlayer metal dielectric film is formed between the first and second metal wire layers. A silicon nitride film serving as a protective insulation film is formed on the fluorinated silicate glass film layer. An adhesive layer made of, for example, a P—SiO film, P—SiON film, or PE—SiO film, is formed between the fluorinated silicate glass film and the silicon nitride film.
    Type: Grant
    Filed: March 12, 2001
    Date of Patent: June 17, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Seiji Okura, Koji Oda, Mahito Sawada
  • Patent number: 6544904
    Abstract: A method of manufacturing a semiconductor device is provided, which prevents a polyimide film from coming unstuck from a film to be subjected to isotropic etching, and further prevents deposits adhered to respective side faces of the films from coming off, during a heat treatment for imidizing the polyimide film. Isotropic etching is performed on a silicon nitride film 4 using, as a mask, a polyimide film 5 having a predetermined pattern formed therein. Next, a heat treatment is carried out to imidize the polyimide film 5 prior to performing anisotropic etching on a silicon oxide film 3. During the heat treatment for imidizing the polyimide film 5, since deposits, which are to be generated by anisotropic etching, are not yet adhered to the respective side faces of the films, the polyimide film 5 does not come unstuck from the silicon nitride film 4. Further, the deposits which are adhered to the respective side face of the films after the heat treatment will not come off.
    Type: Grant
    Filed: May 31, 2002
    Date of Patent: April 8, 2003
    Assignees: Ryoden Semiconductor System Engineering Corporation, Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yuuki Kamiura, Hiroshi Tobimatsu, Kouji Oda, Mahito Sawada, Koji Shibata, Hiroyuki Kawata
  • Publication number: 20020090809
    Abstract: An interconnection is formed on a semiconductor substrate having a semiconductor element formed thereon. Next, a passivation film is formed on the semiconductor substrate including the interconnection. Further, a polyimide film, which is served as a buffer coating film, is formed on the passivation film. Further, the polyimide film is patterned. Next, the passivation film is subject to etching while the patterned polyimide film is taken as a mask. Next, a hardened layer, which is formed on the surface of the polyimide film as a result of etching, is removed through ashing process. Next, the semiconductor substrate after ashing process is cured so as to transform the polyimide film into imide.
    Type: Application
    Filed: July 24, 2001
    Publication date: July 11, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroshi Tobimatsu, Yuuki Kamiura, Seiji Okura, Mahito Sawada
  • Publication number: 20020024145
    Abstract: A plurality of metal wire layers consisting of a first metal wire layer and a second metal wire layer are formed on a semiconductor substrate. A fluorinated silicate glass film serving as an interlayer metal dielectric film is formed between the first and second metal wire layers. A silicon nitride film serving as a protective insulation film is formed on the fluorinated silicate glass film layer. An adhesive layer made of, for example, a P-SiO film, P-SiON film, or PE-SiO film, is formed between the fluorinated silicate glass film and the silicon nitride film.
    Type: Application
    Filed: March 12, 2001
    Publication date: February 28, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Seiji Okura, Koji Oda, Mahito Sawada
  • Patent number: 6213852
    Abstract: A method of manufacturing a semiconductor device using a polishing apparatus is provided. A top ring holding a wafer is arranged on a pad. A polishing chemical liquid supply line for supplying a polishing chemical liquid is arranged above the pad in a direction ahead of rotation with respect to the top ring. Around the center of rotation of the pad, a partition plate having a columnar side surface is arranged. Above the pad on a side which goes away from the top ring when the pad is rotated, a polishing chemical liquid draining mechanism is arranged extending continuously from the partition plate to the outer periphery of the pad. Accordingly, a polishing apparatus is obtained by which the amount of polishing of the surface to be polished of the semiconductor substrate is stabilized and generation of microscratches on the surface to be polished can be suppressed.
    Type: Grant
    Filed: July 12, 1999
    Date of Patent: April 10, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazuyuki Fujii, Takanori Sasaki, Mahito Sawada, Kouichiro Tsutahara