Patents by Inventor Mahmood Khan

Mahmood Khan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140154850
    Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, doped n-type throughout its length, and includes portions serving as gate electrodes of n-channel and p-channel MOS transistors; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. The p-channel MOS transistor includes a buried channel region, formed by way of ion implantation, disposed between its source and drain regions. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.
    Type: Application
    Filed: February 4, 2014
    Publication date: June 5, 2014
    Inventors: Allan T. Mitchell, Imran Mahmood Khan, Michael A. Wu
  • Patent number: 8729616
    Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: May 20, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Imran Mahmood Khan, Allan T. Mitchell, Kaiping Liu
  • Patent number: 8716083
    Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes n-type and p-type doped portions serving as gate electrodes of n-channel and p-channel MOS transistors, respectively; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad. An opening at the surface of the analog floating-gate electrode, at the location at which n-type and p-type doped portions of the floating gate electrode abut, allow formation of silicide at that location, shorting the p-n junction.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: May 6, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Allan T. Mitchell, Imran Mahmood Khan, Michael A. Wu
  • Publication number: 20140001526
    Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. A silicide-block film comprised of a layer of silicon dioxide underlying a top layer of silicon nitride blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit, such as polysilicon-to-metal capacitors, are silicide-clad. Following silicidation, a capacitor dielectric is deposited over the remaining polysilicon structures, followed by formation of an upper metal plate.
    Type: Application
    Filed: June 27, 2012
    Publication date: January 2, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kaiping Liu, Amitava Chatterjee, Imran Mahmood Khan
  • Publication number: 20130341759
    Abstract: An integrated circuit with a high precision MIM capacitor and a high precision resistor with via etch stop landing pads on the resistor heads that are formed with the capacitor bottom plate material. A process of forming an integrated circuit with a high precision MIM capacitor and a high precision resistor where via etch stop landing pads over the resistor heads are formed using the same layer that is used to form the capacitor bottom plate.
    Type: Application
    Filed: June 14, 2013
    Publication date: December 26, 2013
    Applicant: Texas Instruments Incorporated
    Inventors: Imran Mahmood Khan, John Paul Campbell, Neal Thomas Murphy
  • Publication number: 20130334659
    Abstract: An integrated circuit with vias with different depths stopping on etch stop layers with different thicknesses. A method of simultaneously etching vias with different depths without causing etch damage to the material being contacted by the vias.
    Type: Application
    Filed: June 14, 2013
    Publication date: December 19, 2013
    Inventors: Kaiping LIU, Imran Mahmood KHAN, Richard Allen FAUST
  • Publication number: 20130336546
    Abstract: An enclosure works in conjunction with a mobile device to capture biometric identifiers. The mobile device has a screen on a first side and a camera on a second side opposite the first side. The enclosure at least partially covers the mobile device on the first and second sides. The enclosure includes a fingerprint subsystem configured to capture fingerprints with sufficient resolution for biometric identification. The fingerprint subsystem is located on a portion of the enclosure covering the second side of the mobile device. The enclosure includes an iris imaging subsystem configured to capture iris images with sufficient resolution for biometric identification. The iris imaging subsystem includes an iris imaging aperture facing outward from the portion of the enclosure covering the second side of the mobile device. The enclosure includes an electronic data interface configured to communicatively couple the fingerprint and iris imaging subsystems to the mobile device.
    Type: Application
    Filed: June 15, 2012
    Publication date: December 19, 2013
    Applicant: AOPTIX TECHNOLOGIES, INC.
    Inventors: Joseph Justin Pritikin, William Homer Chandler, JR., Fayez Mahmood Khan
  • Publication number: 20130271382
    Abstract: In response to a user selecting a key on a keyboard in a first manner, a first alphanumeric character is displayed on a display device. In response to the user selecting the key on the keyboard in a second manner, a virtual key of a diacritic is displayed on the display device. In response to the user selecting the virtual key of the diacritic on the display device, the diacritic is displayed at a location of a second alphanumeric character on the display device.
    Type: Application
    Filed: April 5, 2013
    Publication date: October 17, 2013
    Applicant: Texas Instruments Incorporated
    Inventor: Sajjad Mahmood Khan
  • Patent number: 8558296
    Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: October 15, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Imran Mahmood Khan, Allan T. Mitchell, Kaiping Liu
  • Publication number: 20130221418
    Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, doped n-type throughout its length, and includes portions serving as gate electrodes of n-channel and p-channel MOS transistors; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. The p-channel MOS transistor includes a buried channel region, formed by way of ion implantation, disposed between its source and drain regions. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.
    Type: Application
    Filed: February 28, 2012
    Publication date: August 29, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Allan T. Mitchell, Imran Mahmood Khan, Michael A. Wu
  • Publication number: 20120330708
    Abstract: The system and method disclosed herein permits hiring managers and jobseekers to receive a ranked list of matching resumes for their posted jobs and resumes respectively. The system administrators and the PerfectMatch Engine validates the jobs and resumes prior to executing the matching process. All users, hiring managers, job seekers and administrators are provided secure access with capability to manage only their data. The validated jobs and resumes are automatically matched by the matching engine creating a ranked list of resumes for each job and jobs for each resume. The job and resume owners are notified of the matches for further action.
    Type: Application
    Filed: December 12, 2011
    Publication date: December 27, 2012
    Inventor: Mahmood A. Khan
  • Publication number: 20120241829
    Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.
    Type: Application
    Filed: March 23, 2011
    Publication date: September 27, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Imran Mahmood Khan, Allan T. Mitchell, Kaiping Liu
  • Publication number: 20120244671
    Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes n-type and p-type doped portions serving as gate electrodes of n-channel and p-channel MOS transistors, respectively; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad. An opening at the surface of the analog floating-gate electrode, at the location at which n-type and p-type doped portions of the floating gate electrode abut, allow formation of silicide at that location, shorting the p-n junction.
    Type: Application
    Filed: January 26, 2012
    Publication date: September 27, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Allan T. Mitchell, Imran Mahmood Khan, Michael A. Wu
  • Patent number: 8178915
    Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes n-type and p-type doped portions serving as gate electrodes of n-channel and p-channel MOS transistors, respectively; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad. An opening at the surface of the analog floating-gate electrode, at the location at which n-type and p-type doped portions of the floating gate electrode abut, allow formation of silicide at that location, shorting the p-n junction.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: May 15, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Allan T. Mitchell, Imran Mahmood Khan, Michael A. Wu
  • Publication number: 20020166391
    Abstract: A device, system and method for bypassing and/or testing a sample of a material flowing in a direction along a flowpath utilizes a sleeve having open ends and defining a duct adapted for insertion into the flowpath and a sidewall. An inlet conduit attached to the sleeve has an inlet section at one end, and an outlet conduit attached to the sleeve has an outlet section. The sample is returned through the outlet conduit in a direction substantially parallel to the direction of the material flowing through the sleeve.
    Type: Application
    Filed: April 4, 2002
    Publication date: November 14, 2002
    Inventors: Khalid Mahmood Khan, Srinivas R. Gadiraju