Patents by Inventor Mahmud Asfur

Mahmud Asfur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190056880
    Abstract: A data storage device includes a controller and a memory. The controller includes a host interface and a memory interface. The controller performs a first operation on the memory through the memory interface at a first frequency associated with the host interface to determine a first data pattern. The controller performs a read operation on the memory through the memory interface at a second frequency to determine a second data pattern. The controller changes the first frequency by a predetermined amount until the first frequency is equal to a maximum operating frequency having an associated risk of a setup/hold violation that is below a predetermined probability.
    Type: Application
    Filed: August 17, 2017
    Publication date: February 21, 2019
    Inventors: Yonatan TZAFRIR, Mordekhay ZEHAVI, Mahmud ASFUR
  • Patent number: 10198383
    Abstract: A device includes a first latch configured to be coupled to a bus and configured to receive a data signal and a clock signal. The device also includes a delay element configured to generate a delayed version of the data signal or a delayed version of the clock signal. A second latch is coupled to the delay element and configured to receive the delayed version of the data signal or the delayed version of the clock signal. The device further includes a comparator coupled to the first latch and the second latch. The comparator is configured to receive a first output from the first latch and a second output from the second latch.
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: February 5, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Mordekhay Zehavi, Yonatan Tzafrir, Mahmud Asfur
  • Publication number: 20180189211
    Abstract: A device includes a first latch configured to be coupled to a bus and configured to receive a data signal and a clock signal. The device also includes a delay element configured to generate a delayed version of the data signal or a delayed version of the clock signal. A second latch is coupled to the delay element and configured to receive the delayed version of the data signal or the delayed version of the clock signal. The device further includes a comparator coupled to the first latch and the second latch. The comparator is configured to receive a first output from the first latch and a second output from the second latch.
    Type: Application
    Filed: December 31, 2016
    Publication date: July 5, 2018
    Inventors: MORDEKHAY ZEHAVI, YONATAN TZAFRIR, MAHMUD ASFUR
  • Patent number: 9996486
    Abstract: A storage device may be configured to adjust a frequency of a clock signal. The clock signal may be associated with a data transfer rate of data to be communicated between a controller and a memory of the storage device. In some implementations, the frequency maybe adjusted responsive to at least one of a supply voltage provided to the storage device, a temperature of the storage device, or a physical characteristic of the storage device.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: June 12, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Mordekhay Zehavi, Mahmud Asfur, Rustam Freidel
  • Patent number: 9720604
    Abstract: Methods and systems are provided where a memory controller for non-volatile memory transfers data to and from random access memory over a second double data rate bus, and a host system access the random access memory over a first double data rate bus. The memory controller may transfer the data in response to a command received by the memory controller from a host system via a block storage protocol bus. Alternatively or in addition, the memory controller may transfer the data as part of caching data internal to the non-volatile memory.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: August 1, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Alex Lemberg, Eyal Sobol, Mahmud Asfur
  • Publication number: 20170124007
    Abstract: A storage device may be configured to adjust a frequency of a clock signal. The clock signal may be associated with a data transfer rate of data to be communicated between a controller and a memory of the storage device. In some implementations, the frequency maybe adjusted responsive to at least one of a supply voltage provided to the storage device, a temperature of the storage device, or a physical characteristic of the storage device.
    Type: Application
    Filed: October 28, 2015
    Publication date: May 4, 2017
    Inventors: Mordekhay Zehavi, Mahmud Asfur, Rustam Freidel
  • Publication number: 20170038982
    Abstract: Methods and systems are provided where a memory controller for non-volatile memory transfers data to and from random access memory over a second double data rate bus, and a host system access the random access memory over a first double data rate bus. The memory controller may transfer the data in response to a command received by the memory controller from a host system via a block storage protocol bus. Alternatively or in addition, the memory controller may transfer the data as part of caching data internal to the non-volatile memory.
    Type: Application
    Filed: August 6, 2015
    Publication date: February 9, 2017
    Inventors: Alex Lemberg, Eyal Sobol, Mahmud Asfur
  • Patent number: 9336130
    Abstract: Methods, systems, and computer readable media for providing BIOS data and non-BIOS data on the same non-volatile memory. According to one aspect, a system for providing BIOS data and non-BIOS data on the same non-volatile memory includes a controller for controlling access by a host to a non-volatile memory for storing data, the data including BIOS data and non-BIOS data. The controller includes a first bus interface for communicating data to and from the host via a first bus of a first bus protocol, a second bus interface for communicating data to and from the host via a second bus of a second bus protocol, and a third interface for communicating data to and from the non-volatile memory. The first bus comprises a bus that is operable after power-on reset and before BIOS is accessed.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: May 10, 2016
    Assignee: SanDisk Technologies Inc.
    Inventors: Mahmud Asfur, Yonatan Tzafrir
  • Publication number: 20130138866
    Abstract: Methods, systems, and computer readable media for providing BIOS data and non-BIOS data on the same non-volatile memory. According to one aspect, a system for providing BIOS data and non-BIOS data on the same non-volatile memory includes a controller for controlling access by a host to a non-volatile memory for storing data, the data including BIOS data and non-BIOS data. The controller includes a first bus interface for communicating data to and from the host via a first bus of a first bus protocol, a second bus interface for communicating data to and from the host via a second bus of a second bus protocol, and a third interface for communicating data to and from the non-volatile memory. The first bus comprises a bus that is operable after power-on reset and before BIOS is accessed.
    Type: Application
    Filed: November 30, 2011
    Publication date: May 30, 2013
    Inventors: Mahmud Asfur, Yonatan Tzafrir
  • Patent number: 8254170
    Abstract: Programmer's data is initially stored in a memory device of the storage device by using an MBC storage scheme. After the storage device is embedded in a host device, the programmer's data is internally read from the memory device by using conventional read reference voltages, and the number of erroneous data bits in the programmer's data is calculated. If the programmer's data includes an uncorrectable number of erroneous data bits, the programmer's data is iteratively reread by using unconventional read reference voltages with decreased levels. The iteration process, which includes decreasing the level of the read reference voltages and recalculating the number of erroneous data bits, is terminated when the number of erroneous data bits in the programmer's is less than or equals a predetermined number of erroneous data bits, after which the storage device restores the programmer's data and conventionally rewrites it into the memory device.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: August 28, 2012
    Assignee: Sandisk IL Ltd.
    Inventors: Yigal Eli, Mahmud Asfur, Shahar Bar-Or
  • Publication number: 20110228604
    Abstract: Programmer's data is initially stored in a memory device of the storage device by using an MBC storage scheme. After the storage device is embedded in a host device, the programmer's data is internally read from the memory device by using conventional read reference voltages, and the number of erroneous data bits in the programmer's data is calculated. If the programmer's data includes an uncorrectable number of erroneous data bits, the programmer's data is iteratively reread by using unconventional read reference voltages with decreased levels. The iteration process, which includes decreasing the level of the read reference voltages and recalculating the number of erroneous data bits, is terminated when the number of erroneous data bits in the programmer's is less than or equals a predetermined number of erroneous data bits, after which the storage device restores the programmer's data and conventionally rewrites it into the memory device.
    Type: Application
    Filed: August 25, 2009
    Publication date: September 22, 2011
    Applicant: SANDISK IL LTD.
    Inventors: Yigal Eli, Mahmud Asfur, Shahar Bar-Or
  • Patent number: 8019923
    Abstract: A card adapter includes a first memory card interface configured to be connected to a first memory card. The first memory card is associated with a first file system. The card adapter includes a second memory card interface that is configured to be connected to a second memory card. The second memory card is associated with a second file system. The card adapter also includes a host interface configured to connect to a host. The card adapter includes a controller operatively interposed between the first and second memory card interfaces and the host interface. The controller is configured to control the first memory card interface and the second memory card interface to control connections between each memory card that is connected thereto with the host. The controller is also configured to operate in each of two selectable modes. In a first mode the controller is operative to emulate a virtual file system that presents to the host the first file system and the second file system as a unified image.
    Type: Grant
    Filed: December 1, 2008
    Date of Patent: September 13, 2011
    Assignee: Sandisk IL Ltd.
    Inventor: Mahmud Asfur
  • Publication number: 20100138580
    Abstract: A card adapter includes a plurality of memory card interfaces for interfacing with a plurality of memory cards, each of the memory cards having its own file system, and a host interface for interfacing a host of the memory cards. A controller of the card adapter interfaces with the plurality of memory card interfaces and with the host interface and controls operation of the memory cards. The card adapter may have several modes of operation, one of which involves emulating, on the host, by the controller, a virtual file system that represents a unified image of the file systems of two or more memory cards. In another mode of operation of the card adapter the controller establishes presents to the host only one file system of a memory card.
    Type: Application
    Filed: December 1, 2008
    Publication date: June 3, 2010
    Applicant: SANDISK IL LTD.
    Inventor: MAHMUD ASFUR