Abstract: An embodiment is a circuit including 2n?1 first comparators to generate a first result by comparing data from at least two of 2n memory cells to which test pattern data are written. 2n?1 first switching circuits provide the first result or a disable signal responsive to a first switching signal. And 2n?2 second comparators generate a second result by comparing signals output from some of the 2n?1 first switching circuits. N may be a natural number greater than or equal to three.

Abstract: An embodiment is a circuit including 2n-1 first comparators to generate a first result by comparing data from at least two of 2n memory cells to which test pattern data are written. 2n-1 first switching circuits provide the first result or a disable signal responsive to a first switching signal. And 2n-2 second comparators generate a second result by comparing signals output from some of the 2n-1 first switching circuits. N may be a natural number greater than or equal to three.

Abstract: A synchronous DRAM and method are provided in which main cells and spare cells are accessed by an external address during automatic refresh of a test mode. In the synchronous DRAM, a mode register setting circuit receives an external signal in response to a plurality of control signals to generate a mode register setting signal, during an automatic refresh operation in a test mode. An address selector selects and outputs an external address to the memory cell array, in response to the activation of the mode register set signal, during the automatic refresh operation in the test mode. The address selector selects and outputs an internal address to the memory cell array, in response to the deactivation of the mode register set signal, during an automatic refresh operation in a normal mode. Therefore, the main cells and the spare cells in the memory cell array are sequentially accessed and refreshed by the external address during the automatic refresh operation in the test mode.