Abstract: Methods, nodes and computer program products control radio channel deployment when using un-licensed carriers in a wireless communication network and control mobility and/or load balancing target selection when using un-licensed carriers. When performed in an access node, unlicensed carrier intrinsic cell channel load is determined in a cell served by the access node based on one or more predetermined channel load indicators and neighbor cell channel load information is obtained, from one or more neighboring access nodes. The neighbor cell channel load information includes unlicensed carrier channel load in respective cells based on the one or more predetermined channel load indicators. At least one channel deployment operation is initiated based on an outcome of one or more comparative operations including the determined unlicensed carrier intrinsic cell channel load and/or the obtained neighbor cell channel load information.

Abstract: The present disclosure is directed to a two-component bonding agent composition and a process for applying a layer of the bonding agent composition to substrate layers to make laminates.

Abstract: Methods, apparatus and systems for wireless motion monitoring to ensure security are described. In one example, a described system comprises: a transmitter configured for transmitting a first wireless signal through a wireless multipath channel of a venue; a receiver configured for receiving a second wireless signal through the wireless multipath channel; and a processor. The second wireless signal differs from the first wireless signal due to the wireless multipath channel and a motion of an object in the venue. The processor is configured for: obtaining a time series of channel information (TSCI) of the wireless multipath channel based on the second wireless signal; computing a spatial-temporal information (STI) based on the TSCI; monitoring the motion of the object based on the TSCI and the STI; performing a task based on the monitoring; and generating a response based on the task.

Abstract: A collimator for a detector is disclosed. The collimator comprises: a bottom plate provided with imaging through holes distributed in an array, each of the imaging through holes comprising a first hole segment and a second hole segment, the transverse size of the first hole segment gradually decreasing in a direction from a free end to the second hole segment, and the transverse size of the second hole segment gradually decreasing in a direction from the free end to the first hole segment; a shielding case formed on the bottom plate; and a top plate disposed in the shielding case and closing at least a part of an opening of the shielding case, the top plate being provided with shielding through holes distributed in an array, and the imaging through holes being in one-to-one correspondence with the shielding through holes.

Abstract: A collimator for a detector is disclosed. The collimator comprises: a bottom plate provided with imaging through holes distributed in an array, each of the imaging through holes comprising a first hole segment and a second hole segment, the transverse size of the first hole segment gradually decreasing in a direction from a free end to the second hole segment, and the transverse size of the second hole segment gradually decreasing in a direction from the free end to the first hole segment; a shielding case formed on the bottom plate; and a top plate disposed in the shielding case and closing at least a part of an opening of the shielding case, the top plate being provided with shielding through holes distributed in an array, and the imaging through holes being in one-to-one correspondence with the shielding through holes.

Abstract: A semiconductor coupon-service system, includes a coupon-service module for managing a semiconductor service; a coupon generator, in connection with the semiconductor service, for generating a coupon associated with the semiconductor service; and a coupon maintainer, in connection with the semiconductor service, for processing coupon operations associated with the coupon.

Abstract: A semiconductor coupon-service system, includes a coupon-service module for managing a semiconductor service; a coupon generator, in connection with the semiconductor service, for generating a coupon associated with the semiconductor service; and a coupon maintainer, in connection with the semiconductor service, for processing coupon operations associated with the coupon.

Abstract: Ion implanted resistors formed in the body of a crystalline silicon substrate. The resistors have a different conductivity type from that of the silicon substrate. The sheet resistance and temperature dependence of the resistor layer is determined by the dose of the implant. Temperature variation can be optimized to be less than 2% over the temperature range ?40 C to +85 C. Furthermore, the temperature variation at room temperature (˜25 C) can be reduced to nearly zero.

Abstract: An impedance network. The network includes a plurality of impedance elements, at least one end terminal, and a wiper terminal. The network also includes a first plurality of switching elements selectively providing tap positions to the at least one end terminal, selectable at a first specified increment of impedance elements in the plurality of impedance elements. The network further includes a second plurality of switching elements selectively providing a tap positions to the wiper terminal, selectable at a second specified increment of impedance elements in the plurality of impedance elements.

Abstract: Ion implanted resistors formed in the body of a crystalline silicon substrate. The resistors have a different conductivity type from that of the silicon substrate. The sheet resistance and temperature dependence of the resistor layer is determined by the dose of the implant. Temperature variation can be optimized to be less than 2% over the temperature range −40 C to +85 C. Furthermore, the temperature variation at room temperature (˜25 C) can be reduced to nearly zero.

Abstract: An impedance network. The network includes a plurality of impedance elements, at least one end terminal, and a wiper terminal. The network also includes a first plurality of switching elements selectively providing tap positions to the at least one end terminal, selectable at a first specified increment of impedance elements in the plurality of impedance elements. The network further includes a second plurality of switching elements selectively providing a tap positions to the wiper terminal, selectable at a second specified increment of impedance elements in the plurality of impedance elements.

Abstract: An impedance network. The network includes a plurality of impedance elements, at least one end terminal, and a wiper terminal. The network also includes a first plurality of switching elements selectively providing tap positions to the at least one end terminal, selectable at a first specified increment of impedance elements in the plurality of impedance elements. The network further includes a second plurality of switching elements selectively providing a tap positions to the wiper terminal, selectable at a second specified increment of impedance elements in the plurality of impedance elements.

Abstract: A method of forming a semiconductor memory having rows and columns of memory cells is as follows; forming a plurality of rows of program gate lines from a second layer polysilicon; forming a plurality of rows of select gate lines from a third polysilicon layer; forming a plurality of rows of diffusion source lines: forming a plurality of local bitlines from a first layer metal, the cells along each column being divided into a pre-designated number of groups, and drains of the cells in each group being connected to a local bitline extending across the cells in the group of cells; and forming a plurality of global bitlines from a second layer metal extending along every two columns of cells, each global bitline being configured to selectively provide electrical connection to the local bitlines along the corresponding two columns of cells.

Abstract: Ion implanted resistors formed in the body of a crystalline silicon substrate. The resistors have a different conductivity type from that of the silicon substrate. The sheet resistance and temperature dependence of the resistor layer is determined by the dose of the implant. Temperature variation can be optimized to be less than 2% over the temperature range −40 C to +85 C. Furthermore, the temperature variation at room temperature (˜25 C) can be reduced to nearly zero.

Abstract: Ion implanted resistors formed in the body of a crystalline silicon substrate. The resistors have a different conductivity type from that of the silicon substrate. The sheet resistance and temperature dependence of the resistor layer is determined by the dose of the implant. Temperature variation can be optimized to be less than 2% over the temperature range −40C to +85C. Furthermore, the temperature variation at room temperature (˜25C) can be reduced to nearly zero.

Abstract: A semiconductor memory includes a plurality of memory cells arranged along rows and columns, each cell having a floating gate, a drain region, a source region, a program gate terminal, and a select gate terminal. The program gate terminals of the cells along each row of cells are connected together forming a continuous program gate line. The select gate terminals of the cells along each row of cells are connected together forming a continuous select gate line. The source regions of the cells along each row of cells are connected together forming a continuous source line. The cells along each column are divided into a predesignated number of groups, and the drain regions of the cells in each group are connected to a local bitline extending across the cells in the group of cells. A global bitline extends along every two columns of cells, and is configured to selectively provide electrical connection to the local bitlines along the corresponding two columns of cells.

Abstract: A field oxide device (FOD) useful for electrostatic discharge (ESD) protection and other applications. The FOD is characterized as being capable of achieving a relatively low breakdown voltage and capable of handling relatively high currents during an ESD event. In general, the FOD includes a zener junction to promote an earlier breakdown of the device. The zener junction also provides a planar-like breakdown region which makes it capable of handling relatively high currents. In particular, the FOD includes a p-doped substrate having a drain-side n+ diffusion region and a source-side n+ diffusion region which are separated by a field oxide. The FOD further includes a p+ doped region that interfaces with the drain-side n+ diffusion region to form a zener junction. The breakdown voltage of the FOD can be easily set by controlling the doping concentration and energy of the p+ doped region.

Abstract: An impedance network. The network includes a plurality of impedance elements, at least one end terminal, and a wiper terminal. The network also includes a first plurality of switching elements selectively providing tap positions to the at least one end terminal, selectable at a first specified increment of impedance elements in the plurality of impedance elements. The network further includes a second plurality of switching elements selectively providing a tap positions to the wiper terminal, selectable at a second specified increment of impedance elements in the plurality of impedance elements.

Abstract: A semiconductor memory includes a plurality of memory cells arranged along rows and columns, each cell having a floating gate, a drain region, a source region, a program gate terminal, and a select gate terminal. The program gate terminals of the cells along each row of cells are connected together forming a continuous program gate line. The select gate terminals of the cells along each row of cells are connected together forming a continuous select gate line. The source regions of the cells along each row of cells are connected together forming a continuous source line. The cells along each column are divided into a predesignated number of groups, and the drain regions of the cells in each group are connected to a local bitline extending across the cells in the group of cells. A global bitline extends along every two columns of cells, and is configured to selectively provide electrical connection to the local bitlines along the corresponding two columns of cells.

Abstract: A method for fabricating a triple self-aligned non-volatile memory device is disclosed. The method includes forming isolation oxide on a substrate. A plurality of floating gates are formed by depositing and self-aligning a first polysilicon layer to the isolation oxide. A common source area is then defined on the substrate between the floating gates. A second polysilicon layer is deposited over the common source area and self-aligned with respect to the isolation oxide. A third polysilicon layer is deposited adjacent to the plurality of floating gates. A plurality of select gates are then formed by self-aligning the third polysilicon layer to the isolation oxide. Furthermore, at least one drain area is defined on the substrate.