Abstract: A semiconductor memory device includes a memory string, a voltage supply circuit, a plurality of control signal lines, a row decoder, and a control circuit. The voltage supply circuit is configured to generate a plurality of operation voltages to operate the semiconductor memory device. The operation voltages include a negative voltage. The plurality of control signal lines is connected between the voltage supply circuit and the memory string. The row decoder includes a plurality of transistors provided in the plurality of control signal lines, respectively. The control circuit is configured to control the transistors of the row decoder, and cause the negative voltage to be supplied to the row decoder during a certain period of time in which a voltage of one of the control signal lines drops to a negative level.

Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.

Abstract: A stator sub-assembly with a connector includes a stator sub-assembly including a stator core and a rigid wiring board, and a connector fixed to a connector mounting part of the rigid wiring board in such a way that it is opposed to the stator core in the radial direction of the frame. A groove part that extends in the axial direction from an opening in the axial direction and accommodates the connector and the connector mounting part is formed in an inner peripheral surface of the frame. A window part for an opponent connector to mate with the connector accommodated in the groove part is formed in the frame. The window part opens in an outer surface of the frame and an inner surface of the groove part, and has an unbroken inner peripheral surface.

Abstract: There is provided a motor armature winding structure that includes a filleted portion including a curved surface, the filleted portion is formed on at least one of corner portions at four corners of a bobbin side wall surface where a wire is wound, and the curved surface has a curvature radius that decreases from a winding start position toward a winding end position in a first layer of the wires wound on the bobbin side wall surface.

Abstract: Provided is a biochemical reaction substrate which can achieve higher test sensitivity and shorter testing time in an allergy test, which can also reduce a required amount of blood or the like needed as a specimen and decrease the number of test steps, thereby facilitating performance of the test, and which is to be used in an allergy test in which infection risk of the test staff is reduced.

Abstract: A semiconductor memory device comprises a first memory cell and a second memory cell. The semiconductor memory device is configured to be able to perform: a first operation which is a read operation or the like to the first memory cell; and a second operation which is a read operation or the like to the second memory cell. The semiconductor memory device transitions to a standby mode after performing the first operation in response to an input of a first command set and a second command set. The semiconductor memory device performs a charge share operation after the standby mode is released in response to an input of a third command set and a fourth command set during the standby mode. The semiconductor memory device performs the second operation using at least a part of an electric charge generated when the first operation is performed.

Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.

Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.

Abstract: A semiconductor memory device includes a memory string, a voltage supply circuit, a plurality of control signal lines, a row decoder, and a control circuit. The voltage supply circuit is configured to generate a plurality of operation voltages to operate the semiconductor memory device. The operation voltages include a negative voltage. The plurality of control signal lines is connected between the voltage supply circuit and the memory string. The row decoder includes a plurality of transistors provided in the plurality of control signal lines, respectively. The control circuit is configured to control the transistors of the row decoder, and cause the negative voltage to be supplied to the row decoder during a certain period of time in which a voltage of one of the control signal lines drops to a negative level.

Abstract: In a frame structure of a motor, when the number of angles of a frame is 4M (M is a natural number, and M?1), and the number of slots of an armature core is 6N (N is a natural number, and N?1), the armature core is inserted into the frame in such a manner as to form a variation ? within a predetermined range in a circumferential direction between a reference line that is orthogonal to two opposing sides of the frame and passes through a rotation axis of the frame, and a straight line linking magnetic poles symmetric about a point with respect to the rotation axis.

Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.

Abstract: A semiconductor storage device includes a memory cell array having a plurality of first conductive layers stacked in a first direction and a plurality of memory cells connected to the plurality of first conductive layers, a wiring layer, and an insulating layer between the memory cell array and the wiring layer and separating the memory cell array and the wiring layer in a second direction intersecting the first direction. The wiring layer includes a plurality of second conductive layers stacked in the first direction, each of the second conductive layers having a corresponding first conductive layer at a same layer, and a contact connected to at least a part of the plurality of second conductive layers and extending in the first direction.

Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.

Abstract: A stator sub-assembly with a connector includes a stator sub-assembly including a stator core and a rigid wiring board, and a connector fixed to a connector mounting part of the rigid wiring board in such a way that it is opposed to the stator core in the radial direction of the frame. A groove part that extends in the axial direction from an opening in the axial direction and accommodates the connector and the connector mounting part is formed in an inner peripheral surface of the frame. A window part for an opponent connector to mate with the connector accommodated in the groove part is formed in the frame. The window part opens in an outer surface of the frame and an inner surface of the groove part, and has an unbroken inner peripheral surface.

Abstract: A bobbin structure of an armature of a three-phase motor having 6N (N is a natural number) slots and 3N coils per phase, the bobbin structure including: a main pole into which a winding bobbin around which a coil is wound is inserted; and an auxiliary pole into which an empty bobbin around which the coil is not wound is inserted. The main pole and the auxiliary pole are placed in a circumferential direction with respect to a rotation axis, and a contact portion where the empty bobbin and the winding bobbin are in contact with each other is formed on each of an outer peripheral side and an inner peripheral side of the slot formed between the main pole and the auxiliary pole.

Abstract: There is provided a motor armature winding structure that includes a filleted portion including a curved surface, the filleted portion is formed on at least one of corner portions at four corners of a bobbin side wail surface where a wire is wound, and the curved surface has a curvature radius that decreases from a winding start position toward a winding end position in a first layer of the wires wound on the bobbin side wall surface.

Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.

Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.

Abstract: An armature molded structure includes a cylindrical iron core used for a molded structure of a motor armature; a winding; and molding resin, wherein the iron core includes first core sheets and second core sheets, the first core sheet includes first magnetic poles placed along a circumferential direction of the iron core, tip portions, on an inner peripheral side of the iron core, of adjacent first magnetic poles form a coupling portion coupling the adjacent first magnetic poles, the second core sheet includes second magnetic poles placed along the circumferential direction of the iron core, tip portions, on the inner peripheral side of the iron core, of adjacent second magnetic poles form a non-coupling portion separating the adjacent second magnetic poles, the first and second core sheets are laminated along a central axis direction of the iron core in such a manner that the coupling portions coincide with each other, the non-coupling portions coincide with each other, the coupling portion and the non-coupl

Abstract: Provided is an armature structure of a three-phase motor which includes: 6N (N is a natural number) slots; 3N coils per phase; 3N main poles; and 3N auxiliary poles.