Abstract: A matrix multiplier circuit which is based on distributed arithmetic is disclosed. In the conventional matrix multiplier circuit, one row of J elements from a data matrix is multiplied in parallel with K columns of elements from a transform matrix to form one row of elements of an output matrix. In contrast, in the inventive matrix multiplier circuit, N rows of elements from the data matrix are multiplied in parallel with K columns of elements from a transform matrix. Maximum advantage of parallel processing and pipelined processing is achieved if N is the nearest integer to M/J where M is the precision of the elements from the data matrix.