Patents by Inventor Majid Aghababazadeh
Majid Aghababazadeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8872297Abstract: A substrate section that is at least partially fabricated to include contact elements and materials. The substrate section includes doped regions that have a heavily doped N-type region and a heavily doped P-type region adjacent to one another. An exterior surface of the substrate has a topography that includes a light-transparent region in which light, from a light source, is able to reach a surface of the substrate. An application of light onto the light transparent region is sufficient to cause a voltage potential to form across a junction of the heavily doped regions. The substrate section may further comprise one or more electrical contacts, positioned on the substrate section to conduct current, resulting from the voltage potential created with application of light onto the light transparent region, to a circuit on the semiconductor substrate.Type: GrantFiled: February 28, 2013Date of Patent: October 28, 2014Assignee: Tau-Metrix, Inc.Inventors: Gary Steinbrueck, James S. Vickers, Mario M. Pelella, Majid Aghababazadeh, Nadar Pakdaman
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Publication number: 20130334644Abstract: A substrate section that is at least partially fabricated to include contact elements and materials. The substrate section includes doped regions that have a heavily doped N-type region and a heavily doped P-type region adjacent to one another. An exterior surface of the substrate has a topography that includes a light-transparent region in which light, from a light source, is able to reach a surface of the substrate. An application of light onto the light transparent region is sufficient to cause a voltage potential to form across a junction of the heavily doped regions. The substrate section may further comprise one or more electrical contacts, positioned on the substrate section to conduct current, resulting from the voltage potential created with application of light onto the light transparent region, to a circuit on the semiconductor substrate.Type: ApplicationFiled: February 28, 2013Publication date: December 19, 2013Applicant: TAU-METRIX, INC.Inventors: Gary Steinbrueck, James S. Vickers, Mario M. Pelella, Majid Aghababazadeh, Nader Pakdaman
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Publication number: 20130210682Abstract: A flow cell including inlet and outlet ports in fluid communication with each other through a flow channel that extends therebetween. The flow channel includes a diffuser region and a field region that is located downstream from the diffuser region. The field region of the flow channel directs fluid along reaction sites where desired reactions occur. The fluid flows through the diffuser region in a first flow direction and through the field region in a second flow direction. The first and second flow directions being substantially perpendicular.Type: ApplicationFiled: October 20, 2011Publication date: August 15, 2013Applicant: Illumina, Inc.Inventors: Helmy A. Eltoukhy, Tarun Khurana, Behnam Javanmardi, Poorya Sabounchi, Majid Aghababazadeh
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Patent number: 8410568Abstract: A substrate section that is at least partially fabricated to include contact elements and materials. The substrate section includes doped regions that have a heavily doped N-type region and a heavily doped P-type region adjacent to one another. An exterior surface of the substrate has a topography that includes a light-transparent region in which light, from a light source, is able to reach a surface of the substrate. An application of light onto the light transparent region is sufficient to cause a voltage potential to form across a junction of the heavily doped regions. The substrate section may further comprise one or more electrical contacts, positioned on the substrate section to conduct current, resulting from the voltage potential created with application of light onto the light transparent region, to a circuit on the semiconductor substrate.Type: GrantFiled: August 25, 2009Date of Patent: April 2, 2013Assignee: Tau-Metrix, Inc.Inventors: Gary Steinbrueck, James S. Vickers, Mario M. Pelella, Majid Aghababazadeh, Nader Pakdaman
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Patent number: 8344745Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of test structures located on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.Type: GrantFiled: August 31, 2006Date of Patent: January 1, 2013Assignee: tau-Metrix, Inc.Inventors: Majid Aghababazadeh, Jose J. Estabil, Nader Pakdaman, Gary L. Steinbrueck, James S. Vickers
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Publication number: 20100304509Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.Type: ApplicationFiled: June 1, 2010Publication date: December 2, 2010Inventors: Majid Aghababazadeh, Jose J. Estabil, Nader Pakdaman, Gary L. Steinbrueck
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Patent number: 7736916Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.Type: GrantFiled: June 14, 2007Date of Patent: June 15, 2010Assignee: tau-Metrix, Inc.Inventors: Majid Aghababazadeh, Jose J. Estabil, Nader Pakdaman, Gary L. Steinbrueck, James S. Vickers
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Patent number: 7730434Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.Type: GrantFiled: August 25, 2004Date of Patent: June 1, 2010Assignee: tau-Metrix, Inc.Inventors: Majid Aghababazadeh, Jose J. Estabil, Nader Pakdaman, Gary L. Steinbrueck
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Patent number: 7723724Abstract: A system is provided for using test structures to evaluate a fabrication of a wafer. The test structures include a combination of device and interconnect elements that are provided on an active region of a die, on the wafer prior to the fabrication of the wafer being completed. The combination of device and interconnect elements include one or more circuits that are activatable to produce an output corresponding to measurable electrical and/or optical characteristics. A power receiving element that is configured to receive activation energy sufficient to cause the output on a contactless medium, so that the activation energy is received without affecting a usability of the die or wafer. The one or more circuits are structured to generate a variation in either the output or in a parameter determined from output, as a result of a process variation in a specific fabrication step that provided elements for forming the one or more circuits.Type: GrantFiled: August 21, 2008Date of Patent: May 25, 2010Assignee: tau-Metrix, Inc.Inventors: Majid Aghababazadeh, Jose J. Estabil, Nader Pakdaman, Gary L. Steinbrueck, James S. Vickers
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Publication number: 20100084729Abstract: A substrate section that is at least partially fabricated to include contact elements and materials. The substrate section includes doped regions that have a heavily doped N-type region and a heavily doped P-type region adjacent to one another. An exterior surface of the substrate has a topography that includes a light-transparent region in which light, from a light source, is able to reach a surface of the substrate. An application of light onto the light transparent region is sufficient to cause a voltage potential to form across a junction of the heavily doped regions. The substrate section may further comprise one or more electrical contacts, positioned on the substrate section to conduct current, resulting from the voltage potential created with application of light onto the light transparent region, to a circuit on the semiconductor substrate.Type: ApplicationFiled: August 25, 2009Publication date: April 8, 2010Inventors: Gary Steinbrueck, James S. Vickers, Mario M. Pelella, Majid Aghababazadeh, Nader Pakdaman
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Patent number: 7605597Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.Type: GrantFiled: November 5, 2007Date of Patent: October 20, 2009Assignee: tau-Metrix, Inc.Inventors: Majid Aghababazadeh, Jose J. Estabil, Nader Pakdaman, Gary L. Steinbrueck, James S. Vickers
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Publication number: 20080315196Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.Type: ApplicationFiled: August 21, 2008Publication date: December 25, 2008Inventors: Majid AGHABABAZADEH, Jose J. Estabil, Nader Pakdaman, Gary L. Steinbrueck, James S. Vickers
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Patent number: 7423288Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter of the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.Type: GrantFiled: April 20, 2007Date of Patent: September 9, 2008Assignee: tau-Metrix, Inc.Inventors: Majid Aghababazadeh, Jose J. Estabil, Nader Pakdaman, Gary L. Steinbrueck, James S. Vickers
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Publication number: 20080100319Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.Type: ApplicationFiled: November 5, 2007Publication date: May 1, 2008Inventors: Majid Aghababazadeh, Jose Estabil, Nader Pakdaman, Gary Steinbrueck, James Vickers
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Patent number: 7339388Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.Type: GrantFiled: August 25, 2004Date of Patent: March 4, 2008Assignee: tau-Metrix, Inc.Inventors: Majid Aghababazadeh, Jose J. Estabil, Nader Pakdaman, Gary L. Steinbrueck, James S. Vickers
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Publication number: 20070238206Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.Type: ApplicationFiled: June 14, 2007Publication date: October 11, 2007Inventors: Majid Aghababazadeh, Jose Estabil, Nader Pakdaman, Gary Steinbrueck, James Vickers
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Publication number: 20070236232Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.Type: ApplicationFiled: June 14, 2007Publication date: October 11, 2007Inventors: Majid Aghababazadeh, Jose Estabil, Nader Pakdaman, Gary Steinbrueck, James Vickers
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Publication number: 20070187679Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter of the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.Type: ApplicationFiled: April 20, 2007Publication date: August 16, 2007Inventors: Majid Aghababazadeh, Jose Estabil, Nader Pakdaman, Gary Steinbrueck, James Vickers
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Patent number: 7256055Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.Type: GrantFiled: August 25, 2004Date of Patent: August 14, 2007Assignee: tau-Metrix, Inc.Inventors: Majid Aghababazadeh, Jose J. Estabil, Nader Pakdaman, Gary L. Steinbrueck, James S. Vickers
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Patent number: 7220990Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.Type: GrantFiled: August 25, 2004Date of Patent: May 22, 2007Assignee: tau-Metrix, Inc.Inventors: Majid Aghababazadeh, Jose J. Estabil, Nader Pakdaman, Gary L. Steinbrueck, James S. Vickers