Patents by Inventor Majid Bemanian
Majid Bemanian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11823434Abstract: A data processing system for generating a fingerprint of an image implements obtaining a first digital image; determining a first fingerprint for the first digital image comprising a first coarse-grain fingerprint element and a first fine-grain fingerprint element by determining the first coarse-grain component based on the first digital image; determining the first fine-grain component based on the first digital image; and generating the first fingerprint by combining the first coarse-grain component with the first-fine grain component; obtaining a second fingerprint for a second digital image, the second fingerprint comprising a second coarse-grain component and a second fine-grain component; comparing the first fingerprint with the second fingerprint to determine a similarity score; and performing one or more actions responsive to the similarity score equaling or exceeding a similarity threshold.Type: GrantFiled: September 21, 2021Date of Patent: November 21, 2023Assignee: DeweyVision Corp.Inventors: Aaron Malcolm Peddle, Majid Bemanian
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Patent number: 11645178Abstract: Techniques are disclosed for processor synchronization within a reconfigurable computing environment for processor array redundancy. Processing elements are configured within a reconfigurable fabric to implement two or more redundant processors, where the two or more redundant processors are enabled for coincident operation. An agent is loaded on each of the two or more redundant processors, where the agent performs a function requiring data validation. The agent is fired on each of the two or more redundant processors to commence coincident operation. The coincident operation can include a lockstep operation. An output data result from each of the two or more redundant processors is compared to enable a data validation result. The data validation result is propagated. The propagating the data validation result can be based on comparing valid output data or can be based on comparing invalid output data.Type: GrantFiled: July 25, 2019Date of Patent: May 9, 2023Assignee: MIPS Tech, LLCInventors: Majid Bemanian, Lawrence H Hudepohl
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Publication number: 20200034262Abstract: Techniques are disclosed for processor synchronization within a reconfigurable computing environment for processor array redundancy. Processing elements are configured within a reconfigurable fabric to implement two or more redundant processors, where the two or more redundant processors are enabled for coincident operation. An agent is loaded on each of the two or more redundant processors, where the agent performs a function requiring data validation. The agent is fired on each of the two or more redundant processors to commence coincident operation. The coincident operation can include a lockstep operation. An output data result from each of the two or more redundant processors is compared to enable a data validation result. The data validation result is propagated. The propagating the data validation result can be based on comparing valid output data or can be based on comparing invalid output data.Type: ApplicationFiled: July 25, 2019Publication date: January 30, 2020Inventors: Majid Bemanian, Lawrence H Hudepohl
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Patent number: 9053951Abstract: An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF.Type: GrantFiled: December 17, 2011Date of Patent: June 9, 2015Inventors: Majid Bemanian, Farhang Yazdani
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Patent number: 9035443Abstract: An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF. Various examples are also given for different implementations.Type: GrantFiled: November 27, 2011Date of Patent: May 19, 2015Inventors: Majid Bemanian, Farhang Yazdani
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Patent number: 8390035Abstract: An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF.Type: GrantFiled: May 6, 2009Date of Patent: March 5, 2013Inventors: Majid Bemanian, Farhang Yazdani
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Publication number: 20120086050Abstract: An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF.Type: ApplicationFiled: December 17, 2011Publication date: April 12, 2012Inventors: Majid Bemanian, Farhang Yazdani
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Publication number: 20120068229Abstract: An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF. Various examples are also given for different implementations.Type: ApplicationFiled: November 27, 2011Publication date: March 22, 2012Inventors: Majid Bemanian, Farhang Yazdani
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Publication number: 20100283085Abstract: An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF.Type: ApplicationFiled: May 6, 2009Publication date: November 11, 2010Inventors: Majid Bemanian, Farhang Yazdani
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Patent number: 7831653Abstract: A partially manufactured semiconductor chip comprising a slice and a number of shells is a template for a communication and networking chip. The slice has a number of I/O ports, blocks, and PHYs. The hardmac PHYs are established to correspond to a high speed data transmission protocol. The interior of the template comprises logic gate arrays and configurable memory. Once particular protocols of data receipt and transmission are selected, the logic gate arrays and configurable memory can be programmed and otherwise configured to develop protocol layers for data networking and communication.Type: GrantFiled: December 13, 2002Date of Patent: November 9, 2010Assignee: LSI CorporationInventors: George Wayne Nation, Gary Scott Delp, William D. Scharf, Narayanan Raman, John N. Fryar, III, Majid Bemanian
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Patent number: 7233604Abstract: A time division media access controller for use with a multi-port data switch and a method of controlling media access. In one embodiment, the time division media access controller includes a time division receive engine, a time division transmit engine and a time division arbiter coupled to the time division receive and transmit engines. The time division receive engine accepts data from a plurality of data ports and the time division transmit engine provides data to a plurality of data ports. The time division arbiter controls states of the time division receive and transmit engines based on throughput requirements of the data. In preferred embodiments, the time division media access controller complies with the IEEE 802.3 ethernet standard.Type: GrantFiled: June 4, 2002Date of Patent: June 19, 2007Assignee: LSI CorporationInventors: Majid Bemanian, Narayanan Raman
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Patent number: 6934597Abstract: An integrated circuit (IC) and a method of manufacturing an integrated circuit suited for a particular application. In one embodiment, the IC includes: (1) at least two interfaces, (2) a programmable gate array (PGA) coupled to the at least two interfaces for communicating data therebetween and, optionally (3) a field-programmable gate array (FPGA) coupled to and configured to cooperate with the PGA to adapt the IC to a particular surrounding environment.Type: GrantFiled: March 26, 2002Date of Patent: August 23, 2005Assignee: LSI Logic CorporationInventors: Majid Bemanian, William D. Scharf
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Patent number: 6904586Abstract: An integrated circuit (IC) and a method of manufacturing an integrated circuit suited for a particular application. In one embodiment, the IC includes at least two interfaces, a field-programmable gate array (FPGA) and a programmable gate array (PGA). The FPGA has a configuration memory associated therewith and is coupled to the at least two interfaces for communicating data therebetween. The PGA is coupled to and configured to cooperate with the FPGA to adapt the IC to a particular surrounding environment.Type: GrantFiled: March 25, 2002Date of Patent: June 7, 2005Assignee: LSI Logic CorporationInventors: Majid Bemanian, William D. Scharf, Bruce L. Entin
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Publication number: 20040114622Abstract: A partially manufactured semiconductor chip comprising a slice and a number of shells is a template for a communication and networking chip. The slice has a number of I/O ports, blocks, and PHYs. The hardmac PHYs are established to correspond to a high speed data transmission protocol. The interior of the template comprises logic gate arrays and configurable memory. Once particular protocols of data receipt and transmission are selected, the logic gate arrays and configurable memory can be programmed and otherwise configured to develop protocol layers for data networking and communication.Type: ApplicationFiled: December 13, 2002Publication date: June 17, 2004Applicant: LSI Logic CorporationInventors: George Wayne Nation, Gary Scott Delp, William D. Scharf, Narayanan Raman, John N. Fryar, Majid Bemanian
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Patent number: 5857087Abstract: A pipelined bus which can support more than one channel between data sources and data destinations at a time. The bus includes an arbitration bus, a command bus and a data bus. In accordance with the bus protocol, different channels may access the various bus components in the same clock cycle. For example, the data source of one channel may issue a command on the command bus to its selected data destination to get ready to receive data while at the same time, a data source of a second channel actually transmits data on the data bus to its selected data destination. During the same clock cycle, a third data source can be selected by the arbitration bus to initiate or resume a channel.Type: GrantFiled: August 25, 1997Date of Patent: January 5, 1999Assignee: Timeplex, Inc.Inventors: Majid Bemanian, John Bailey
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Patent number: 5809258Abstract: A pipelined bus which can support more than one channel between data sources and data destinations at a time. The bus includes an arbitration bus, a command bus and a data bus. In accordance with the bus protocol, different channels may access the various bus components in the same clock cycle. For example, the data source of one channel may issue a command on the command bus to its selected data destination to get ready to receive data while at the same time, a data source of a second channel actually transmits data on the data bus to its selected data destination. During the same clock cycle, a third data source can be selected by the arbitration bus to initiate or resume a channel.Type: GrantFiled: January 6, 1997Date of Patent: September 15, 1998Assignee: Ascom Timeplex Trading AGInventors: Majid Bemanian, John Bailey
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Patent number: 5600450Abstract: A film correction system adjusts a relative position of film containing an area for information and a scanner of the film area. The system includes a scanner for scanning the film area at a film plane. A film drive moves the film along the film plane. A focused beam separate from the film area scanner scans a film edge in the film for determining a location of the film edge. A circuit is coupled to the focused beam scanner for changing a relative position of the film area scanner and the film area. The film edge scanner is a flying spot scanner, and the apparatus includes signal processors for processing the sprocket information. The system may be retrofit to an existing telecine apparatus. A separate coil may be used to provide deflection of a flying spot scanner used to scan the picture information on the film.Type: GrantFiled: August 25, 1995Date of Patent: February 4, 1997Assignee: MSCL, Inc.Inventors: Michael C. Kaye, Majid Bemanian
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Patent number: 5555092Abstract: A film correction system adjusts a relative position of film containing an area for information and a scanner of the film area. The system includes a scanner for scanning the film area at a film plane. A film drive moves the film along the film plane. A focused beam separate from the film area scanner scans a film edge in the film for determining a location of the film edge. A circuit is coupled to the focused beam scanner for changing a relative position of the film area scanner and the film area. The film edge scanner is a flying spot scanner, and the apparatus includes signal processors for processing the sprocket information. The system may be retrofit to an existing telecine apparatus. A separate coil may be used to provide deflection of a flying spot scanner used to scan the picture information on the film.Type: GrantFiled: October 18, 1988Date of Patent: September 10, 1996Assignee: MSCLInventors: Michael C. Kaye, Majid Bemanian
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Patent number: 5430478Abstract: A film correction system adjusts a relative position of film containing an area for information and a scanner of the film area. The system includes a scanner for scanning the film area at a film plane, A film drive moves the film along the film plane. A focused beam separate from the film area scanner scans a film edge in the film for determining a location of the film edge. A circuit is coupled to the focused beam scanner for changing a relative position of the film area scanner and the film area. The film edge scanner is a flying spot scanner, and the apparatus includes signal processors for processing the sprocket information. The system may be retrofit to an existing telecine apparatus. A separate coil may be used to provide deflection of a flying spot scanner used to scan the picture information on the film.Type: GrantFiled: June 24, 1994Date of Patent: July 4, 1995Assignee: MSCL, Inc.Inventors: Michael C. Kaye, Majid Bemanian
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Patent number: 5089882Abstract: A processor includes an input for receiving video color component signals, and a circuit for deriving a luminance signal and a color magnitude signal from the video color component signals. A further circuit is provided for modifying at least one of the luminance and color magnitude signals whenever a composite video signal derived from the luminance signal in the color magnitude signal has a magnitude which exceeds a predetermined value. An output is provided for producing color component signals derived from the luminance and color magnitude signals from the modifying circuit.Type: GrantFiled: September 8, 1989Date of Patent: February 18, 1992Assignee: MSCL, Inc.Inventors: Michael C. Kaye, Majid Bemanian