Abstract: A system and method for the predictive maintenance of electronic components that includes sensors at at least one position via which present values of system parameters, such as temperature and voltage, and a signal propagation time at the at least one position are determined, where values of the system parameters and the signal propagation time presently determined by the sensors are retrieved by a central monitoring unit, an individual valid limit value is determined for the signal propagation time at each of the at least one position via the central monitoring unit based on the presently determined values of the system parameters, and the presently determined signal propagation time at each of the at least one position is compared with the associated valid limit value, and a notification is sent to a superordinate level, if the signal propagation time exceeds the limit value to trigger replacement of the electronic component.

Abstract: A system and method for the predictive maintenance of electronic components that includes sensors at at least one position via which present values of system parameters, such as temperature and voltage, and a signal propagation time at the at least one position are determined, where values of the system parameters and the signal propagation time presently determined by the sensors are retrieved by a central monitoring unit, an individual valid limit value is determined for the signal propagation time at each of the at least one position via the central monitoring unit based on the presently determined values of the system parameters, and the presently determined signal propagation time at each of the at least one position is compared with the associated valid limit value, and a notification is sent to a superordinate level, if the signal propagation time exceeds the limit value to trigger replacement of the electronic component.

Abstract: A method for adjusting a pull resistor on a contact terminal of an electronic module arranged on a printed circuit board, in particular an ASIC, after initiating a restart of the electronic module which, during a run-up process, moves the electronic module from a switched-off state into a switched-on state, wherein after initiating a restart during the run-up process from a partial circuit arranged on the electronic module and operationally ready during the run-up process, adjustment information relating to a desired adjustment of the pull resistor is retrieved from a storage unit arranged on the printed circuit board outside of the electronic module and transmitted via a contact line between the electronic module and the storage unit, where the run-up process of the electronic module is only completed after successful adjustment of the respective pull resistor based on basis the retrieved adjustment information.

Abstract: A circuit arrangement and method for temporally limiting and separating access between at least one master unit and at least one slave unit via a network-on-a-chip bus system in a system-on-a-chip, wherein the access between the at least one master and slave units is implemented via communication paths defined by bus interfaces, where within the circuit arrangement, the network-on-a-chip bus system is expanded by an adaptation unit that includes an access manager and a complementary logic for the bus interfaces, where the adaptation unit and the bus interfaces are then controlled by the access manager via the complementary logic using a communication plan such that access between the master and slave units via the communication paths specified by bus interfaces is performed in accordance with the temporal requirements of the communication plan so that time-controlled systems can be implemented simply using commercially obtainable standard bus systems.

Abstract: A method for protecting an integrated circuit against unauthorized access to key registers, wherein functions and/or applications of the integrated circuit are unlocked and/or activated via data stored in key registers, such as during the start-up of the integrated circuit and/or during ongoing operation, where if such a key register is accessed, the data word used to perform the access is compared with specified key data, and if access via a data word deviating from the specified key data is detected, the access is marked as unauthorized, the access marked as unauthorized is then recorded and evaluated, and after the analysis, appropriate protective measures are triggered to prevent further unauthorized access such that a key register method for protecting sensitive data is expanded in a simple manner and hacker attacks are quickly detected and thwarted.

Abstract: A circuit arrangement and method for securing an integrated electronic circuit against scans of an address space, wherein the circuit arrangement has at least one master unit and at least one slave unit interconnected via a bus system for access of the master unit to the slave unit, and addresses are used from an address space that is allocated and used in accordance with functionalities of the integrated electronic circuit, where a defense slave unit is connected to the bus system, access to unused address regions of the address space are forwarded to the defense slave unit, the access is analyzed and evaluated by the defense slave unit and depending on an analysis result and the respective access type, defensive measures are triggered, such that address space scans are interrupted or a potential scan result is rendered useless in a simple manner.

Abstract: A method for adjusting a pull resistor on a contact terminal of an electronic module arranged on a printed circuit board, in particular an ASIC, after initiating a restart of the electronic module which, during a run-up process, moves the electronic module from a switched-off state into a switched-on state, wherein after initiating a restart during the run-up process from a partial circuit arranged on the electronic module and operationally ready during the run-up process, adjustment information relating to a desired adjustment of the pull resistor is retrieved from a storage unit arranged on the printed circuit board outside of the electronic module and transmitted via a contact line between the electronic module and the storage unit, where the run-up process of the electronic module is only completed after successful adjustment of the respective pull resistor based on basis the retrieved adjustment information.

Abstract: A method for protecting an integrated circuit against unauthorized access to key registers, wherein functions and/or applications of the integrated circuit are unlocked and/or activated via data stored in key registers, such as during the start-up of the integrated circuit and/or during ongoing operation, where if such a key register is accessed, the data word used to perform the access is compared with specified key data, and if access via a data word deviating from the specified key data is detected, the access is marked as unauthorized, the access marked as unauthorized is then recorded and evaluated, and after the analysis, appropriate protective measures are triggered to prevent further unauthorized access such that a key register method for protecting sensitive data is expanded in a simple manner and hacker attacks are quickly detected and thwarted.

Abstract: A circuit arrangement and method for temporally limiting and separating access between at least one master unit and at least one slave unit via a network-on-a-chip bus system in a system-on-a-chip, wherein the access between the at least one master and slave units is implemented via communication paths defined by bus interfaces, where within the circuit arrangement, the network-on-a-chip bus system is expanded by an adaptation unit that includes an access manager and a complementary logic for the bus interfaces, where the adaptation unit and the bus interfaces are then controlled by the access manager via the complementary logic using a communication plan such that access between the master and slave units via the communication paths specified by bus interfaces is performed in accordance with the temporal requirements of the communication plan so that time-controlled systems can be implemented simply using commercially obtainable standard bus systems.

Abstract: A circuit arrangement and method for securing an integrated electronic circuit against scans of an address space, wherein the circuit arrangement has at least one master unit and at least one slave unit interconnected via a bus system for access of the master unit to the slave unit, and addresses are used from an address space that is allocated and used in accordance with functionalities of the integrated electronic circuit, where a defense slave unit is connected to the bus system, access to unused address regions of the address space are forwarded to the defense slave unit, the access is analyzed and evaluated by the defense slave unit and depending on an analysis result and the respective access type, defensive measures are triggered, such that address space scans are interrupted or a potential scan result is rendered useless in a simple manner.

Abstract: A circuit arrangement and method for accessing slave units in a system on chip in a controlled manner, wherein an access of a master unit of the system on chip to one of the slave units is performed via a network-on-chip bus system using an access address, where a memory protection unit is integrated between the at least one master unit and the network-on-chip bus system, and access authorization of the master unit to a slave unit is checked by the memory protection unit by comparing the access address with specified address sections, and when an unauthorized access of the master unit to a slave unit is identified, the access address is modified by the memory protection unit such that the unauthorized access is terminated in the network-on-chip bus system.

Abstract: In an application-specific integrated circuit (ASIC), a description of the logic circuit is formulated in a hardware description language and then converted into a description of a corresponding physical circuit, i.e., into a netlist, using a conversion program, i.e., a synthesis tool. The description at least largely consisting of standard cells. During the conversion process, the standard cells which are used in the netlist are replaced with standard cell versions which have a correspondingly balanced power dissipation. Spying on a mode of operation of the circuit by analyzing a power consumption of the circuit is thus advantageously hindered or prevented, in particular in security-relevant circuits.

Abstract: An IC including duplicated primary components which can be operated microsynchronously has at least one synchronization device for synchronizing asynchronous signals to the primary clock. An asynchronous signal intended for the primary components is routed via the synchronization device, synchronized and supplied to the inputs of the primary components. With duplicated asynchronous components, an output signal from just one asynchronous component is synchronized and is supplied to the primary components.

Abstract: The invention relates to an electronic component with an integrated semiconductor circuit that comprises a core with functional flip-flops. A part of the functional flip-flops is linked as input flip-flops with input pins of the component and a part of the functional flip-flops is linked as output flip-flops with output pins of the component. In order to allow for efficient and cost-effective ASIC qualification methods that can be carried out rapidly and that take into consideration the growing complexity of integrated circuits and the rapid development of technology, the invention provides a method and a device wherein the input flip-flops and the output flip-flops are interconnected to a shift register during a qualification measurement of the component.

Abstract: According to the invention, the aim of an optimisation of the timing in normal mode with no disadvantage to, or limitation of the scanning mode may be achieved for an electronic component with an integrated circuit comprising output flip-flops, the output data of which in the normal mode of the component is transmitted to an output buffer on the component, controlled by a control signal, the control signal being provided in normal mode by an output-enable flip-flop provided for the output buffer and in a scan mode for the component by scan-enable cells. Said aim is achieved, whereby a device is provided, in which in the scan mode, a scan-enable cell controls at least two output buffers.

Abstract: The invention relates to an electronic component comprising an integrated circuit that is provided with a core with functional flip-flops. A part of the functional flip-flops are linked as input flip-flops with input pins of the component and a part of the functional flip-flops are linked as output flip-flops with output pins of the component. The aim of the invention is to fulfill high timing requirements while not complicating the verification of timing and logic. For this purpose, the input flip-flops and the output flip-flops are arranged in such a manner that they form at least input block and one output block each with respective clock domains that differ from the clock domains of the remaining core.

Abstract: With methods for developing an electronic component, in which a layout is executed for a component and a file is also generated with timing information, the present invention avoids the superfluous net list changes by providing the following steps: a) Executing an initial timing analysis using the file to identify violations of timing requirements; b) Producing the chip in accordance with the current layout, if no timing violations were detected, otherwise c) Saving information about violations of the timing requirements identified in at least one patch list; d) Changing the file in accordance with the violation information in the patch list; e) Executing the timing analysis again using the modified file; f) Iteration of Steps c), d) and e), if a new timing violation was established; g) When no more timing violations are established, executing a layout adaptation step and generating a new file containing runtime information based on the adapted layout; and h) Returning to Step a) and executing the step.

Abstract: A method for testing an emulated logic circuit is described wherein a model of the logic circuit is loaded into a hardware emulator (EM) and there put into an operating mode in which flip-flops it contains are functionally chained into one or more shift registers. The structural arrangement of the logic circuit in the hardware emulator (EM) is subsequently compared with the structural arrangement of the model of the logic circuit with the assistance of this operating mode. A device for implementing the method is also described.

Abstract: The present invention, in addition to the number of connections required for the specified functions of an ASIC, provides an application specific module ASIC that has additional connections as spares for subsequent modification. Buffers, boundary scan devices and, possibly, basic logic function, are reserved for the additional connections, which may be arranged in a geometrically uniform distribution and which are intended as inputs or as outputs. In the event of a redesign, in particular in the event of only minor design corrections, the effort development costs and time is considerably reduced.

Abstract: A processor device includes a clock generation unit, a processor unit, a main memory, a processor bus, and also a bus control device having an interface for a crossover bus to at least one further processor device. The bus control device monitors processor device data access through the processor bus, interchanges signals concerning data access through the crossover bus, evaluates them and outputs an error signal based on the evaluation result. In a processor system including at least two processor devices connected to one another through the crossover bus, the processor units are started in synchronism. The bus control devices in the processor devices interchange signals through the crossover bus upon each data access operation by the processor units, and output an error signal if there is no correspondence. If there is an error in one processor device, operation of the processor system is continued on the other processor device or devices.