Patents by Inventor Makar SNAI

Makar SNAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11595007
    Abstract: An active feedback low-noise amplifier includes a feedback transistor whose source couples through a feedback path to an input signal node. A bias transistor biases the source of the feedback transistor with a bias current responsive to an input signal carried on the input signal node.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: February 28, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Makar Snai, Manohar Seetharam
  • Publication number: 20220131505
    Abstract: An active feedback low-noise amplifier includes a feedback transistor whose source couples through a feedback path to an input signal node. A bias transistor biases the source of the feedback transistor with a bias current responsive to an input signal carried on the input signal node.
    Type: Application
    Filed: October 27, 2020
    Publication date: April 28, 2022
    Inventors: Makar SNAI, Manohar SEETHARAM
  • Patent number: 10790805
    Abstract: An impedance converter circuit achieves negative capacitance and/or negative inductance for radio frequency (RF) front end impedance matching for low noise amplifier (LNA) designs. The impedance converter circuit includes a first transistor coupled to a first RF input at a source of the first transistor. The impedance converter circuit also includes a second transistor coupled to a second RF input at a source of the second transistor. The second transistor is cross-coupled to the first transistor to form a cross-coupled pair of transistors. The cross-coupled pair of transistors is configured to generate a negative capacitance or a negative inductance based on a load impedance coupled to a drain of the first transistor and a drain of the second transistor.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: September 29, 2020
    Assignee: QUALCOMM Incorporated
    Inventor: Makar Snai
  • Patent number: 10581385
    Abstract: Certain aspects of the present disclosure are directed to a circuit for signal processing. The circuit generally includes a first transformer having a first inductive element magnetically coupled with a second inductive element, and a second transformer having a third inductive element magnetically coupled with a fourth inductive element, wherein the first inductive element is coupled in series with the third inductive element. In certain aspects, the circuit also includes a first switch coupled in parallel with the third inductive element, a capacitive element coupled in parallel with the fourth inductive element, wherein a notch is formed at least by the capacitive element and the fourth inductive element, the notch circuit coupled in series with the second inductive element, and a second switch coupled in parallel with the fourth inductive element.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: March 3, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Makar Snai, Manohar Seetharam, Ehab Abdel Ghany, Vinod Panikkath
  • Publication number: 20200036345
    Abstract: Certain aspects of the present disclosure are directed to a circuit for signal processing. The circuit generally includes a first transformer having a first inductive element magnetically coupled with a second inductive element, and a second transformer having a third inductive element magnetically coupled with a fourth inductive element, wherein the first inductive element is coupled in series with the third inductive element. In certain aspects, the circuit also includes a first switch coupled in parallel with the third inductive element, a capacitive element coupled in parallel with the fourth inductive element, wherein a notch is formed at least by the capacitive element and the fourth inductive element, the notch circuit coupled in series with the second inductive element, and a second switch coupled in parallel with the fourth inductive element.
    Type: Application
    Filed: July 23, 2019
    Publication date: January 30, 2020
    Inventors: Makar SNAI, Manohar SEETHARAM, Ehab ABDEL GHANY, Vinod PANIKKATH
  • Patent number: 10541654
    Abstract: Amplification with post-distortion compensation is disclosed. In an example aspect, an apparatus includes a voltage rail and a cascode amplifier. The cascode amplifier includes an amplification node, a cascode node, and a common-source node. The cascode amplifier also includes at least one cascode transistor, an input transistor, and a compensation transistor. The cascode transistor is coupled between the amplification node and the cascode node. The input transistor is coupled between the cascode node and the common-source node. The compensation transistor is coupled between the voltage rail and the cascode node.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: January 21, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Makar Snai, Ehab Abdel Ghany, Manohar Seetharam, Li-chung Chang
  • Publication number: 20200014340
    Abstract: Amplification with post-distortion compensation is disclosed. In an example aspect, an apparatus includes a voltage rail and a cascode amplifier. The cascode amplifier includes an amplification node, a cascode node, and a common-source node. The cascode amplifier also includes at least one cascode transistor, an input transistor, and a compensation transistor. The cascode transistor is coupled between the amplification node and the cascode node. The input transistor is coupled between the cascode node and the common-source node. The compensation transistor is coupled between the voltage rail and the cascode node.
    Type: Application
    Filed: July 9, 2018
    Publication date: January 9, 2020
    Inventors: Makar Snai, Ehab Abdel Ghany, Manohar Seetharam, Li-chung Chang
  • Patent number: 10419045
    Abstract: Certain aspects of the present disclosure generally relate to a circuit for signal processing. The circuit generally includes a first transformer having a first inductive element magnetically coupled with a second inductive element, and a second transformer having a third inductive element magnetically coupled with a fourth inductive element. In certain aspects, the first inductive element may be coupled in series with the third inductive element. In certain aspects, the circuit also includes a capacitive element coupled in parallel with the fourth inductive element, the capacitive element and the fourth inductive element forming a notch circuit, the notch circuit coupled in series with the second inductive element.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: September 17, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Makar Snai, Manohar Seetharam, Ehab Abdel Ghany, Vinod Panikkath
  • Patent number: 10164591
    Abstract: Certain aspects of the present disclosure provide methods and apparatus for amplifying signals with an amplification circuit and improving a common-mode rejection ratio (CMRR) thereof. The amplification circuit generally includes a differential amplifier comprising a first pair of transistors and a second pair of transistors coupled to the first pair of transistors, where the gates of the first pair of transistors are coupled to respective differential input nodes. The amplification circuit also includes an auxiliary amplifier comprising a third pair of transistors corresponding to the first pair of transistors and a fourth pair of transistors corresponding to the second pair of transistors, where drains of the third and fourth pairs of transistors are coupled together and to gates of the second pair of transistors and where gates of the fourth pair of transistors are coupled together.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: December 25, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Makar Snai, Tonmoy Biswas
  • Publication number: 20180337660
    Abstract: An impedance converter circuit achieves negative capacitance and/or negative inductance for radio frequency (RF) front end impedance matching for low noise amplifier (LNA) designs. The impedance converter circuit includes a first transistor coupled to a first RF input at a source of the first transistor. The impedance converter circuit also includes a second transistor coupled to a second RF input at a source of the second transistor. The second transistor is cross-coupled to the first transistor to form a cross-coupled pair of transistors. The cross-coupled pair of transistors is configured to generate a negative capacitance or a negative inductance based on a load impedance coupled to a drain of the first transistor and a drain of the second transistor.
    Type: Application
    Filed: August 9, 2017
    Publication date: November 22, 2018
    Inventor: Makar SNAI