Patents by Inventor Makarand Karmarkar

Makarand Karmarkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Nanostructured films and related methods
    Patent number: 9057144
    Abstract: Nanostructured films including a plurality of nanowells, the nanowells having a pore at the top surface of the film, the pore defining a channel that extends downwardly towards the bottom surface of the film are provided. Also provided are methods including exposing a growth substrate to an anodizing bath, applying ultrasonic vibrations to the anodizing bath, and generating a current through the anodizing bath to form the nanostructured film. The nanostructured films may be formed from TiO2 and may be used to provide solid state dye sensitized solar cells having high conversion efficiencies.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: June 16, 2015
    Assignee: UNIVERSITY OF UTAH RESEARCH FOUNDATION
    Inventors: Ashutosh Tiwari, Michael Snure, Makarand Karmarkar
  • NANOSTRUCTURED FILMS AND RELATED METHODS
    Publication number: 20130161614
    Abstract: Nanostructured films including a plurality of nanowells, the nanowells having a pore at the top surface of the film, the pore defining a channel that extends downwardly towards the bottom surface of the film are provided. Also provided are methods including exposing a growth substrate to an anodizing bath, applying ultrasonic vibrations to the anodizing bath, and generating a current through the anodizing bath to form the nanostructured film. The nanostructured films may be formed from TiO2 and may be used to provide solid state dye sensitized solar cells having high conversion efficiencies.
    Type: Application
    Filed: July 29, 2011
    Publication date: June 27, 2013
    Inventors: Ashutosh Tiwari, Michael Snure, Makarand Karmarkar
  • PIN structures including intrinsic gallium arsenide, devices incorporating the same, and related methods
    Patent number: 8431928
    Abstract: Provided herein are PIN structures including a layer of amorphous n-type silicon, a layer of intrinsic GaAs disposed over the layer of amorphous n-type silicon, and a layer of amorphous p-type silicon disposed over the layer of intrinsic GaAs. The layer of intrinsic GaAs may be engineered by the disclosed methods to exhibit a variety of structural properties that enhance light absorption and charge carrier mobility, including oriented polycrystalline intrinsic GaAs, embedded particles of intrinsic GaAs, and textured surfaces. Also provided are devices incorporating the PIN structures, including photovoltaic devices.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: April 30, 2013
    Assignee: The University of Utah Research Foundation
    Inventors: Ashutosh Tiwari, Makarand Karmarkar, Nathan Wheeler Gray
  • PIN structures including intrinsic gallium arsenide, devices incorporating the same, and related methods
    Patent number: 8164092
    Abstract: Provided herein are PIN structures including a layer of amorphous n-type silicon, a layer of intrinsic GaAs disposed over the layer of amorphous n-type silicon, and a layer of amorphous p-type silicon disposed over the layer of intrinsic GaAs. The layer of intrinsic GaAs may be engineered by the disclosed methods to exhibit a variety of structural properties that enhance light absorption and charge carrier mobility, including oriented polycrystalline intrinsic GaAs, embedded particles of intrinsic GaAs, and textured surfaces. Also provided are devices incorporating the PIN structures, including photovoltaic devices.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: April 24, 2012
    Assignee: The University of Utah Research Foundation
    Inventors: Ashutosh Tiwari, Makarand Karmarkar, Nathan Wheeler Gray
  • PIN STRUCTURES INCLUDING INTRINSIC GALLIUM ARSENIDE, DEVICES INCORPORATING THE SAME, AND RELATED METHODS
    Publication number: 20120086007
    Abstract: Provided herein are PIN structures including a layer of amorphous n-type silicon, a layer of intrinsic GaAs disposed over the layer of amorphous n-type silicon, and a layer of amorphous p-type silicon disposed over the layer of intrinsic GaAs. The layer of intrinsic GaAs may be engineered by the disclosed methods to exhibit a variety of structural properties that enhance light absorption and charge carrier mobility, including oriented polycrystalline intrinsic GaAs, embedded particles of intrinsic GaAs, and textured surfaces. Also provided are devices incorporating the PIN structures, including photovoltaic devices.
    Type: Application
    Filed: December 15, 2011
    Publication date: April 12, 2012
    Inventors: Ashutosh Tiwari, Makarand Karmarkar, Nathan Wheeler Gray
  • PIN STRUCTURES INCLUDING INTRINSIC GALLIUM ARSENIDE, DEVICES INCORPORATING THE SAME, AND RELATED METHODS
    Publication number: 20110175085
    Abstract: Provided herein are PIN structures including a layer of amorphous n-type silicon, a layer of intrinsic GaAs disposed over the layer of amorphous n-type silicon, and a layer of amorphous p-type silicon disposed over the layer of intrinsic GaAs. The layer of intrinsic GaAs may be engineered by the disclosed methods to exhibit a variety of structural properties that enhance light absorption and charge carrier mobility, including oriented polycrystalline intrinsic GaAs, embedded particles of intrinsic GaAs, and textured surfaces. Also provided are devices incorporating the PIN structures, including photovoltaic devices.
    Type: Application
    Filed: January 12, 2011
    Publication date: July 21, 2011
    Inventors: Ashutosh Tiwari, Makarand Karmarkar, Nathan Wheeler Gray