Patents by Inventor Makarand Yashwant Joshi

Makarand Yashwant Joshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Simulation and timing control for hardware accelerated simulation
    Patent number: 7257524
    Abstract: A fully synthesizeable Simulation Control Module (SCM) controls and monitors the simulation of a design under test (DUT). A clock generator within the SCM and a Software clock facility residing on the host workstation are responsible for providing the clocks for the DUT. The SCM and the hardware clock facility are dynamically generated at build time to suit the needs of the DUT. They maximize performance by automatically generating clock waveforms for designs containing multiple asynchronous clocks, thereby decreasing the frequency of accelerator-workstation interaction. The software clock facility has the ability to directly drive the DUT and is responsible for managing the simulation time and clock parameters. The SCM is also responsible for monitoring an abort condition such as a trigger to execute an external software model. The SCM and the clock facilities allow the hardware accelerator to efficiently support multiple asynchronous clock domains, execution of external software models and co-simulation.
    Type: Grant
    Filed: September 18, 2002
    Date of Patent: August 14, 2007
    Assignee: Quickturn Design Systems, Inc.
    Inventors: William John Schilp, Pramodini Arramreddy, Krishna Babu Bangera, Makarand Yashwant Joshi
  • Simulation and timing control for hardware accelerated simulation
    Publication number: 20030171908
    Abstract: A fully synthesizeable Simulation Control Module (SCM) controls and monitors the simulation of a design under test (DUT). A clock generator within the SCM and a Software clock facility residing on the host workstation are responsible for providing the clocks for the DUT. The SCM and the hardware clock facility are dynamically generated at build time to suit the needs of the DUT. They maximize performance by automatically generating clock waveforms for designs containing multiple asynchronous clocks, thereby decreasing the frequency of accelerator-workstation interaction. The software clock facility has the ability to directly drive the DUT and is responsible for managing the simulation time and clock parameters. The SCM is also responsible for monitoring an abort condition such as a trigger to execute an external software model. The SCM and the clock facilities allow the hardware accelerator to efficiently support multiple asynchronous clock domains, execution of external software models and co-simulation.
    Type: Application
    Filed: September 18, 2002
    Publication date: September 11, 2003
    Applicant: Quickturn Design Systems, Inc.
    Inventors: William John Schilp, Pramodini Arramreddy, Krishna Babu Bangera, Makarand Yashwant Joshi