Abstract: A plurality of metal interconnects incorporating dielectric spacers and a method to form such dielectric spacers are described. In one embodiment, the dielectric spacers adjacent to neighboring metal interconnects are discontiguous from one another. In another embodiment, the dielectric spacers may provide a region upon which un-landed vias may effectively land.

Abstract: An out-of-band illumination filter for use in photolithography in the form of a top coat on a photoresist is described. The top coat may used by applying a photoresist to a substrate, applying a top coat to the photoresist to prevent out-of-band illumination from exposing the photoresist, and exposing the photoresist in a lithography tool.

Abstract: A method of forming an interconnection that includes introducing a barrier material in a via of a dielectric to a circuit device on a substrate in such a manner to deposit the barrier material on the circuit device, introducing a seed material into the via in manner that leaves the barrier material overlying the circuit device substantially exposed, substantially removing the barrier material overlying the circuit device, and introducing a conductive material into the via to form the interconnection.

Abstract: A damascene process using a doped and undoped oxide ILD is described. The selectivity between the carbon doped and carbon free oxide provides an etching stop between the ILD's in addition to providing mechanical strength to the structure.

Abstract: Embodiments of the invention provide a method for producing ferroelectric polymer devices (FPMDs) employing conditions that avoid or reduce detrimental impact on the ferroelectric polymer film. For one embodiment, a damascene patterning metallization technique is used. For one embodiment a first metal layer is deposited on a substrate to form the bottom electrode for the FPMD. The first metal layer is capped with a selectively deposited diffusion barrier. A layer of ferroelectric polymer film is then deposited on the first conductive layer. The ferroelectric polymer film is planarized. A second metal layer is deposited on the ferroelectric polymer film layer to form the top electrode of the FPMD. The second metal layer is deposited such that the ferroelectric polymer film is not substantially degraded. For various alternative embodiments the various component processes may be accomplished at temperatures far below those employed in a conventional damascene patterning metallization process.

Abstract: Embodiments of the invention provide a method for producing ferroelectric polymer devices (FPMDs) employing conditions that avoid or reduce detrimental impact on the ferroelectric polymer film. For one embodiment, a damascene patterning metallization technique is used. For one embodiment a first metal layer is deposited on a substrate to form the bottom electrode for the FPMD. The first metal layer is capped with a selectively deposited diffusion barrier. A layer of ferroelectric polymer film is then deposited on the first conductive layer. The ferroelectric polymer film is planarized. A second metal layer is deposited on the ferroelectric polymer film layer to form the top electrode of the FPMD. The second metal layer is deposited such that the ferroelectric polymer film is not substantially degraded. For various alternative embodiments the various component processes may be accomplished at temperatures far below those employed in a conventional damascene patterning metallization process.

Abstract: In some embodiments, the invention provides a stress mitigation layer that reduces stress in a layer of a microelectronic device that is below a conductive connection structure, such as a bump.

Abstract: Multiple level interconnect structures and methods for fabricating the interconnect structures are disclosed. The interconnect structures may contain an interconnect line, an electrolessly deposited metal layer formed over the interconnect line, a via formed over the metal layer, and a second interconnect line formed over the via. Often the metal layer contains a cobalt or nickel alloy and provides an etch stop layer for formation of an opening corresponding to the via. The metal layer may provide protection to the underlying interconnect line and may replace a traditional protective dielectric layer. The metal layer is conductive, rather than dielectric, and provides a shunt for passage of electrical current between the via and the interconnect line. Similar metal layers may also be used within the interconnect structures as via liner layers and via plugs.

Abstract: Apparatus and methods in accordance with the present invention utilize thermoelectric cooling (TEC) technology to provide enhanced power distribution and/or dissipation from a microelectronic die and/or microelectronic packages. Individual TEC devices are thermally interconnected with the microelectronic die in a number of placement configurations, including between the microelectronic die and the heat sink, on the integrated heat spreader (IHS) inner surface, and on the IHS outer surface. TEC devices comprise p- and n-type semiconducting material created using similar process as the microcircuits. The TEC devices are located in various regions within or on the microelectronic die, including directly below the microcircuits, on the backside of the microelectronic die, and on a separate substrate of microelectronic die material fabricated apart from the microelectronic die and subsequently thermally coupled to the backside of the microelectronic die.

Abstract: In some embodiments, the invention provides a stress mitigation layer that reduces stress in a layer of a microelectronic device that is below a conductive connection structure, such as a bump.

Abstract: Multiple level interconnect structures and methods for fabricating the interconnect structures are disclosed. The interconnect structures may contain an interconnect line, an electrolessly deposited metal layer formed over the interconnect line, a via formed over the metal layer, and a second interconnect line formed over the via. Often the metal layer contains a cobalt or nickel alloy and provides an etch stop layer for formation of an opening corresponding to the via. The metal layer may provide protection to the underlying interconnect line and may replace a traditional protective dielectric layer. The metal layer is conductive, rather than dielectric, and provides a shunt for passage of electrical current between the via and the interconnect line. Similar metal layers may also be used within the interconnect structures as via liner layers and via plugs.

Abstract: An absorbing composition is described herein that includes at least one inorganic-based compound, at least one absorbing compound, and at least one material modification agent. In addition, methods of making an absorbing composition are also described that includes: a) combining at least one inorganic-based compound, at least one absorbing compound, at least one material modification agent, an acid/water mixture, and one or more solvents to form a reaction mixture; and b) allowing the reaction mixture to form the absorbing composition at room temperature. Another method of making an absorbing composition includes: a) combining at least one inorganic-based compound, at least one absorbing compound, at least one material modification agent, an acid/water mixture, and one or more solvents to form a reaction mixture; and b) heating the reaction mixture to form the absorbing composition.

Abstract: A damascene process using a doped and undoped oxide ILD is described. The selectivity between the carbon doped and carbon free oxide provides an etching stop between the ILD's in addition to providing mechanical strength to the structure.

Abstract: A method of forming an air gap intermetal layer dielectric (ILD) to reduce capacitive coupling between electrical conductors in proximity. The method entails forming first and second electrical conductors over a substrate, wherein the electrical conductors are laterally spaced apart by a gap. Then, forming a gap bridging dielectric layer that extends over the first electrical conductor, the gap, and the second electrical conductor. In order to form a bridge from one electrical conductor to the other electrical conductor, the gap bridging dielectric materials should have poor gap filling characteristics. This can be attained by selecting and/or modifying a dielectric material to have a sufficiently high molecular weight and/or surface tension characteristic such that the material does not substantially sink into the gap. An example of such a material is a spin-on-polymer with a surfactant and/or other additives.

Abstract: Embodiments of the invention provide a method for producing ferroelectric polymer devices (FPMDs) employing conditions that avoid or reduce detrimental impact on the ferroelectric polymer film. For one embodiment, a damascene patterning metallization technique is used. For one embodiment a first metal layer is deposited on a substrate to form the bottom electrode for the FPMD. The first metal layer is capped with a selectively deposited diffusion barrier. A layer of ferroelectric polymer film is then deposited on the first conductive layer. The ferroelectric polymer film is planarized. A second metal layer is deposited on the ferroelectric polymer film layer to form the top electrode of the FPMD. The second metal layer is deposited such that the ferroelectric polymer film is not substantially degraded. For various alternative embodiments the various component processes may be accomplished at temperatures far below those employed in a conventional damascene patterning metallization process.

Abstract: Embodiments of the invention provide a method for producing ferroelectric polymer devices (FPMDs) employing conditions that avoid or reduce detrimental impact on the ferroelectric polymer film. For one embodiment, a damascene patterning metallization technique is used. For one embodiment a first metal layer is deposited on a substrate to form the bottom electrode for the FPMD. The first metal layer is capped with a selectively deposited diffusion barrier. A layer of ferroelectric polymer film is then deposited on the first conductive layer. The ferroelectric polymer film is planarized. A second metal layer is deposited on the ferroelectric polymer film layer to form the top electrode of the FPMD. The second metal layer is deposited such that the ferroelectric polymer film is not substantially degraded. For various alternative embodiments the various component processes may be accomplished at temperatures far below those employed in a conventional damascene patterning metallization process.

Abstract: Embodiments of the invention provide a method for producing ferroelectric polymer devices (FPMDs) employing conditions that avoid or reduce detrimental impact on the ferroelectric polymer film. For one embodiment, a damascene patterning metallization technique is used. For one embodiment a first metal layer is deposited on a substrate to form the bottom electrode for the FPMD. The first metal layer is capped with a selectively deposited diffusion barrier. A layer of ferroelectric polymer film is then deposited on the first conductive layer. The ferroelectric polymer film is planarized. A second metal layer is deposited on the ferroelectric polymer film layer to form the top electrode of the FPMD. The second metal layer is deposited such that the ferroelectric polymer film is not substantially degraded. For various alternative embodiments the various component processes may be accomplished at temperatures far below those employed in a conventional damascene patterning metallization process.

Abstract: A cleaning composition comprises at least quaternary ammonium hydroxide, a water-soluble organic solvent, water, an anticorrosive, and potassium hydroxide of 1 mass percent or less of a total amount of the solution. This cleaning composition can singly and effectively remove a photoresist film, a buried material, a metallic residue from the surface of a semiconductor substrate.

Abstract: A method of integrating a polymeric interlayer dielectric. The method comprises forming a dielectric layer comprising a polymer on a conductive layer formed on a substrate. A sacrificial hard mask is then formed on the dielectric layer. A first photoresist layer is then patterned on the sacrificial hard mask to define a first etched region, which is formed through the dielectric layer while substantially all of the first photoresist layer is removed. A sacrificial fill layer then covers the sacrificial hard mask and fills the first etched region. A second photoresist layer is patterned over the sacrificial fill layer to define a second etched region which is formed through the sacrificial fill layer and the dielectric layer while substantially all of the second photoresist layer and the sacrificial fill layer are simultaneously removed.

Abstract: Apparatus and methods in accordance with the present invention utilize thermoelectric cooling (TEC) technology to provide enhanced power distribution and/or dissipation from a microelectronic die and/or microelectronic packages. Individual TEC devices are thermally interconnected with the microelectronic die in a number of placement configurations, including between the microelectronic die and the heat sink, on the integrated heat spreader (IHS) inner surface, and on the IHS outer surface. TEC devices comprise p- and n-type semiconducting material created using similar process as the microcircuits. The TEC devices are located in various regions within or on the microelectronic die, including directly below the microcircuits, on the backside of the microelectronic die, and on a separate substrate of microelectronic die material fabricated apart from the microelectronic die and subsequently thermally coupled to the backside of the microelectronic die.