Patents by Inventor Maki MOROI

Maki MOROI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR DEVICE
    Publication number: 20230352392
    Abstract: A semiconductor device includes: a chip; a circuit element formed in the chip; an insulating layer formed over the chip so as to cover the circuit element; a multilayer wiring region formed in the insulating layer and including a plurality of wirings laminated and arranged in a thickness direction of the insulating layer so as to be electrically connected to the circuit element; at least one insulating region which does not include the wirings in an entire region in the thickness direction of the insulating layer and is formed in a region outside the multilayer wiring region in the insulating layer; and at least one terminal electrode disposed over the insulating layer so as to face the chip with the at least one insulating region interposed between the at least one terminal electrode and the chip.
    Type: Application
    Filed: July 7, 2023
    Publication date: November 2, 2023
    Inventors: Hiroaki MATSUBARA, Kaori SUMITOMO, Maki MOROI, Naoki KINOSHITA
  • Semiconductor device
    Patent number: 11735511
    Abstract: A semiconductor device includes: a chip; a circuit element formed in the chip; an insulating layer formed over the chip so as to cover the circuit element; a multilayer wiring region formed in the insulating layer and including a plurality of wirings laminated and arranged in a thickness direction of the insulating layer so as to be electrically connected to the circuit element; at least one insulating region which does not include the wirings in an entire region in the thickness direction of the insulating layer and is formed in a region outside the multilayer wiring region in the insulating layer; and at least one terminal electrode disposed over the insulating layer so as to face the chip with the at least one insulating region interposed between the at least one terminal electrode and the chip.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: August 22, 2023
    Assignee: ROHM CO., LTD.
    Inventors: Hiroaki Matsubara, Kaori Sumitomo, Maki Moroi, Naoki Kinoshita
  • SEMICONDUCTOR DEVICE
    Publication number: 20220020678
    Abstract: A semiconductor device includes: a chip; a circuit element formed in the chip; an insulating layer formed over the chip so as to cover the circuit element; a multilayer wiring region formed in the insulating layer and including a plurality of wirings laminated and arranged in a thickness direction of the insulating layer so as to be electrically connected to the circuit element; at least one insulating region which does not include the wirings in an entire region in the thickness direction of the insulating layer and is formed in a region outside the multilayer wiring region in the insulating layer; and at least one terminal electrode disposed over the insulating layer so as to face the chip with the at least one insulating region interposed between the at least one terminal electrode and the chip.
    Type: Application
    Filed: July 1, 2021
    Publication date: January 20, 2022
    Inventors: Hiroaki MATSUBARA, Kaori SUMITOMO, Maki MOROI, Naoki KINOSHITA