Patents by Inventor Maki Shimoda

Maki Shimoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8383396
    Abstract: Disclosed is a biomolecular detection device that can be used easily, at a low operating cost, and with a detection probe that can be immobilized easily. Using an insulated gate field effect transistor having a conductive electrode on the gate insulator between a source and a drain, a probe for detecting biomolecules is immobilized on the surface of the conductive electrode. For analysis, a conductive electrode on which a probe for detecting biomolecules is immobilized on the surface, and a reference electrode are placed in the sample solution in the analytical cell, an alternating current voltage is applied from a power source to the reference electrode and the electrical characteristics of the insulated gate field effect transistor that changes before and after binding of the measurement target substance such as DNA and proteins included in the sample solution with a probe for detecting biomolecules, namely the changes in the current values running between the source and the drain, are detected.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: February 26, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Masao Kamahori, Yoshiaki Yazawa, Maki Shimoda
  • Patent number: 7397104
    Abstract: A semiconductor integrated circuit device is provided which includes an active region, a shallow groove isolation adjacent to the active region, and a semiconductor element formed in the active region and having a gate. The sum of a width of the active region and a width of the shallow groove isolation constitutes a minimum pitch in the direction of a gate width of the gate, and the width of the active region is set larger than one-half of the minimum pitch.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: July 8, 2008
    Assignee: Elpida Memory, Inc.
    Inventors: Norio Suzuki, Hiroyuki Ichizoe, Masayuki Kojima, Keiji Okamoto, Shinichi Horibe, Kozo Watanabe, Yasuko Yoshida, Shuji Ikeda, Akira Takamatsu, Norio Ishitsuka, Atsushi Ogishima, Maki Shimoda
  • Publication number: 20060223170
    Abstract: A biomolecule detecting element capable of easily immobilizing a detecting probe and being used in a simple manner without requiring a dark box and the like. A biomolecule detecting probe is immobilized on the surface of a conductive electrode of an insulated gate field effect transistor, the conductive electrode being formed on the surface of a gate insulating material between a source and a drain. Portions other than the conductive electrode are covered with a light-shielding member so as to eliminate the influence of light. During measurement, the conductive electrode having a biomolecule detecting probe immobilized on the surface thereof and a reference electrode are disposed in a buffer solution in a measurement cell.
    Type: Application
    Filed: January 11, 2006
    Publication date: October 5, 2006
    Inventors: Masao Kamahori, Yu Ishige, Maki Shimoda
  • Publication number: 20060016699
    Abstract: Disclosed is a biomolecular detection device that can be used easily, at a low operating cost, and with a detection probe that can be immobilized easily. Using an insulated gate field effect transistor having a conductive electrode on the gate insulator between a source and a drain, a probe for detecting biomolecules is immobilized on the surface of the conductive electrode. For analysis, a conductive electrode on which a probe for detecting biomolecules is immobilized on the surface, and a reference electrode are placed in the sample solution in the analytical cell, an alternating current voltage is applied from a power source to the reference electrode and the electrical characteristics of the insulated gate field effect transistor that changes before and after binding of the measurement target substance such as DNA and proteins included in the sample solution with a probe for detecting biomolecules, namely the changes in the current values running between the source and the drain, are detected.
    Type: Application
    Filed: March 7, 2005
    Publication date: January 26, 2006
    Inventors: Masao Kamahori, Yoshiaki Yazawa, Maki Shimoda
  • Publication number: 20040214428
    Abstract: Conductive layers are formed in the trenches made in an insulating film in the following manner. First, an amorphous silicon film 26A is deposited in the trenches 25 made in a silicon oxide film 24. A photoresist film 30 is then formed on the amorphous silicon film 26A by means of spin coating. Then, exposure light is applied to the entire surface of the photoresist film 30, thereby exposing to light those parts of the photoresist film 30 which lie outside the trenches 25. The other parts of the photoresist film 30, which lie in the trenches 25 are not exposed to light because the light reaching them is inadequate. Further, the photoresist film 30 is developed thereby removing those parts of the film 30 which lie outside the trenches 25 and which have been exposed to light. Thereafter, those parts of the amorphous silicon film 26A, which lie outside the trenches 25, are removed by means of dry etching using, as a mask, the unexposed parts of the photoresist film 30 which remain in the trenches 25.
    Type: Application
    Filed: May 17, 2004
    Publication date: October 28, 2004
    Applicants: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Ryouichi Furukawa, Kazuyuki Suko, Masayuki Hiranuma, Koichi Saitoh, Hirohiko Yamamoto, Tadanori Yoshida, Masayuki Ishizaka, Maki Shimoda
  • Publication number: 20040159883
    Abstract: A semiconductor integrated circuit device is provided which includes an active region, a shallow groove isolation adjacent to the active region, and a semiconductor element formed in the active region and having a gate. The sum of a width of the active region and a width of the shallow groove isolation constitutes a minimum pitch in the direction of a gate width of the gate, and the width of the active region is set larger than one-half of the minimum pitch.
    Type: Application
    Filed: February 17, 2004
    Publication date: August 19, 2004
    Inventors: Norio Suzuki, Hiroyuki Ichizoe, Masayuki Kojima, Keiji Okamoto, Shinichi Horibe, Kozo Watanabe, Yasuko Yoshida, Shuji Ikeda, Akira Takamatsu, Norio Ishitsuka, Atsushi Ogishima, Maki Shimoda
  • Patent number: 6770528
    Abstract: Conductive layers are formed in the trenches made in an insulating film in the following manner. First, an amorphous silicon film 26A is deposited in the trenches 25 made in a silicon oxide film 24. A photoresist film 30 is then formed on the amorphous silicon film 26A by means of spin coating. Then, exposure light is applied to the entire surface of the photoresist film 30, thereby exposing to light those parts of the photoresist film 30 which lie outside the trenches 25. The other parts of the photoresist film 30, which lie in the trenches 25 are not exposed to light because the light reaching them is inadequate. Further, the photoresist film 30 is developed thereby removing those parts of the film 30 which lie outside the trenches 25 and which have been exposed to light. Thereafter, those parts of the amorphous silicon film 26A, which lie outside the trenches 25, are removed by means of dry etching using, as a mask, the unexposed parts of the photoresist film 30 which remain in the trenches 25.
    Type: Grant
    Filed: February 19, 2003
    Date of Patent: August 3, 2004
    Assignees: Hitachi ULSI Systems Co., Ltd., Renesas Technology Corp.
    Inventors: Ryouichi Furukawa, Kazuyuki Suko, Masayuki Hiranuma, Koichi Saitoh, Hirohiko Yamamoto, Tadanori Yoshida, Masayuki Ishizaka, Maki Shimoda
  • Patent number: 6720234
    Abstract: Grooves are defined in a substrate having device isolation regions by dry etching using silicon nitride films and side wall spacers as masks. Thereafter, the side wall spacers lying on side walls of the silicon nitride films are removed and the substrate is subjected to thermal oxidation, whereby the surface of the substrate at a peripheral portion of each active region is subjected to so-called round processing so as to have a sectional shape having a convex rounded shape.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: April 13, 2004
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Norio Suzuki, Hiroyuki Ichizoe, Masayuki Kojima, Keiji Okamoto, Shinichi Horibe, Kozo Watanabe, Yasuko Yoshida, Shuji Ikeda, Akira Takamatsu, Norio Ishitsuka, Atsushi Ogishima, Maki Shimoda
  • Publication number: 20030148600
    Abstract: Conductive layers are formed in the trenches made in an insulating film in the following manner. First, an amorphous silicon film 26A is deposited in the trenches 25 made in a silicon oxide film 24. A photoresist film 30 is then formed on the amorphous silicon film 26A by means of spin coating. Then, exposure light is applied to the entire surface of the photoresist film 30, thereby exposing to light those parts of the photoresist film 30 which lie outside the trenches 25. The other parts of the photoresist film 30, which lie in the trenches 25 are not exposed to light because the light reaching them is inadequate. Further, the photoresist film 30 is developed thereby removing those parts of the film 30 which lie outside the trenches 25 and which have been exposed to light. Thereafter, those parts of the amorphous silicon film 26A, which lie outside the trenches 25, are removed by means of dry etching using, as a mask, the unexposed parts of the photoresist film 30 which remain in the trenches 25.
    Type: Application
    Filed: February 19, 2003
    Publication date: August 7, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Ryouichi Furukawa, Kazuyuki Suko, Masayuki Hiranuma, Koichi Saitoh, Hirohiko Yamamoto, Tadanori Yoshida, Masayuki Ishizaka, Maki Shimoda
  • Publication number: 20030148587
    Abstract: Grooves are defined in a substrate having device isolation regions by dry etching using silicon nitride films and side wall spacers as masks. Thereafter, the side wall spacers lying on side walls of the silicon nitride films are removed and the substrate is subjected to thermal oxidation, whereby the surface of the substrate at a peripheral portion of each active region is subjected to so-called round processing so as to have a sectional shape having a convex rounded shape.
    Type: Application
    Filed: February 14, 2003
    Publication date: August 7, 2003
    Inventors: Norio Suzuki, Hiroyuki Ichizoe, Masayuki Kojima, Keiji Okamoto, Shinichi Horibe, Kozo Watanabe, Yasuko Yoshida, Shuji Ikeda, Akira Takamatsu, Norio Ishitsuka, Atsushi Ogishima, Maki Shimoda
  • Patent number: 6562695
    Abstract: Grooves are defined in a substrate having device isolation regions by dry etching using silicon nitride films and side wall spacers as masks. Thereafter, the side wall spacers lying on side walls of the silicon nitride films are removed and the substrate is subjected to thermal oxidation, whereby the surface of the substrate at a peripheral portion of each active region is subjected to so-called round processing so as to have a sectional shape having a convex rounded shape.
    Type: Grant
    Filed: July 10, 2001
    Date of Patent: May 13, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Norio Suzuki, Hiroyuki Ichizoe, Masayuki Kojima, Keiji Okamoto, Shinichi Horibe, Kozo Watanabe, Yasuko Yoshida, Shuji Ikeda, Akira Takamatsu, Norio Ishitsuka, Atsushi Ogishima, Maki Shimoda
  • Patent number: 6444405
    Abstract: Conductive layers are formed in the trenches made in an insulating film in the following manner. First, an amorphous silicon film 26A is deposited in the trenches 25 made in a silicon oxide film 24. A photoresist film 30 is then formed on the amorphous silicon film 26A by means of spin coating. Then, exposure light is applied to the entire surface of the photoresist film 30, thereby exposing to light those parts of the photoresist film 30 which lie outside the trenches 25. The other parts of the photoresist film 30, which lie in the trenches 25 are not exposed to light because the light reaching them is inadequate. Further, the photoresist film 30 is developed thereby removing those parts of the film 30 which lie outside the trenches 25 and which have been exposed to light. Thereafter, those parts of the amorphous silicon film 26A, which lie outside the trenches 25, are removed by means of dry etching using, as a mask, the unexposed parts of the photoresist film 30 which remain in the trenches 25.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: September 3, 2002
    Assignees: Hitachi, Ltd., Hitachi Ulsi Systems Co., LTD
    Inventors: Ryouichi Furukawa, Kazuyuki Suko, Masayuki Hiranuma, Koichi Saitoh, Hirohiko Yamamoto, Tadanori Yoshida, Masayuki Ishizaka, Maki Shimoda
  • Publication number: 20020098678
    Abstract: Conductive layers are formed in the trenches made in an insulating film in the following manner. First, an amorphous silicon film 26A is deposited in the trenches 25 made in a silicon oxide film 24. A photoresist film 30 is then formed on the amorphous silicon film 26A by means of spin coating. Then, exposure light is applied to the entire surface of the photoresist film 30, thereby exposing to light those parts of the photoresist film 30 which lie outside the trenches 25. The other parts of the photoresist film 30, which lie in the trenches 25 are not exposed to light because the light reaching them is inadequate. Further, the photoresist film 30 is developed thereby removing those parts of the film 30 which lie outside the trenches 25 and which have been exposed to light. Thereafter, those parts of the amorphous silicon film 26A, which lie outside the trenches 25, are removed by means of dry etching using, as a mask, the unexposed parts of the photoresist film 30 which remain in the trenches 25.
    Type: Application
    Filed: April 2, 2002
    Publication date: July 25, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Ryouichi Furukawa, Kazuyuki Suko, Masayuki Hiranuma, Koichi Saitoh, Hirohiko Yamamoto, Tadanori Yoshida, Masayuki Ishizaka, Maki Shimoda
  • Publication number: 20010009177
    Abstract: A system and method for two-sided etch of a semiconductor substrate. Reactive species are generated and flowed toward a substrate for processing. A diverter is positioned between the generation chamber and the substrate. A portion of the reactive species flows through the diverter for processing the front of the substrate. Another portion is diverted around the substrate to the backside for processing. A flow restricter is placed between the substrate and the exhaust system to increase the residence time of reactive species adjacent to the backside.
    Type: Application
    Filed: July 12, 1999
    Publication date: July 26, 2001
    Inventors: LAIZHONG LUO, YING HOLDEN, RENE GEORGE, ROBERT GUERRA, ALLAN WEISNOSKI, NICOLE KUHL, CRAIG RANFT, SAI MANTRIPRAGADA, MASAYUKI KOJIMA, MAKI SHIMODA, TAKAHIRO CHIBA, HIDEYUKI SUGA, KAZUBIKO KAWAI
  • Patent number: 5747387
    Abstract: According to the present invention, the surface of the sample is cleaned with water immediately after ashing of the resist the quality of which has been changed through ion implantation by ozone-containing gas, or ozone-containing gas and ultraviolet ray, or the sample is cleaned with water without being exposed to the atmosphere after ashing, thereby allowing the number of residues to be reduced to 1/100, decreasing the load in cleaning process by solution, cutting down the semiconductor device production cost and improving the semiconductor device productivity.
    Type: Grant
    Filed: August 25, 1995
    Date of Patent: May 5, 1998
    Assignees: Hitachi, Ltd., Hitachi Microcomputer System Ltd.
    Inventors: Koutarou Koizumi, Sukeyoshi Tsunekawa, Kazuhiko Kawai, Maki Shimoda, Katsuhiko Itoh, Haruo Itoh, Akio Saito