Abstract: Provided are a stent to be placed in the bile duct and a process for producing the stent, the stent hollow being less apt to be blocked even when the stent is placed in the bile duct for a long period. The inner peripheral surface of the stent is coated with a resin layer with resistance to sludge formation that includes a polymer obtained by polymerizing 2-methoxyethyl acrylate. This stent is produced by applying a coating fluid that contains 0.1-0.5 mass % polymer obtained by polymerizing 2-methoxyethyl acrylate, to the inner peripheral surface of a stent.

Abstract: Provided are a stent to be placed in the bile duct and a process for producing the stent, the stent hollow being less apt to be blocked even when the stent is placed in the bile duct for a long period. The inner peripheral surface of the stent is coated with a resin layer with resistance to sludge formation that includes a polymer obtained by polymerizing 2-methoxyethyl acrylate. This stent is produced by applying a coating fluid that contains 0.1-0.5 mass % polymer obtained by polymerizing 2-methoxyethyl acrylate, to the inner peripheral surface of a stent.

Abstract: The present invention semiconductor memory device includes common signal lines from which memory cell data is read and an amplifier for detecting a potential difference between these common signal lines, wherein equalization of the common signal lines is started when a potential difference required for an operation of the amplifier is generated on the common signal lines.Also, a semiconductor memory device having a plurality of memory cell arrays includes first common signal lines for reading memory cell data and second common signal lines having the first common signal lines connected thereto. The first common signal lines are operated in an activated state only after a writing operation, whereby access time of the semiconductor device can be shortened.

Abstract: The present invention semiconductor memory device includes common signal lines from which memory cell data is read and an amplifier for detecting a potential difference between these common signal lines, wherein equalization of the common signal lines is started when a potential difference required for an operation of the amplifier is generated on the common signal lines. Also, a semiconductor memory device having a plurality of memory cell arrays includes first common signal lines for reading memory cell data and second common signal lines having the first common signal lines connected thereto. The first common signal lines are operated in an activated state only after a writing operation, whereby access time of the semiconductor device can be shortened.

Abstract: Read data supplied from one of a plurality of differential amplifier circuits is transmitted to a read data bus driver circuit via one of a plurality of CMOS transfer gates and a data latch circuit. The potential of read data bus pair is forcedly set to a low level in response to a control signal until the read data is transmitted to the read data bus driver circuit. Thereafter, the read data bus driver circuit drives the read data bus pair in accordance with the transmitted read data. Thereby, a speed of the address access operation can be increased without outputting invalid data.