Abstract: A point management system using a vehicle as a contact point includes: an evaluation device that evaluates a specific activity of an user of the vehicle based on vehicle information according to a travel state of the vehicle or activity information recorded in a smart device of the user; a point giving device that gives the point to the user according to an evaluation by the evaluation device; and a propose device that proposes, to the user, an activity for which the point is given. The specific activity includes at least one of three categories of an eco-driving activity, a health care activity, and a social contribution activity.

Abstract: An arithmetic processing apparatus includes a controlling unit that refers to an attribute of a compressing scheme on data on a main memory when the data is transferred between the main memory and a memory controller, and that transfers the data by switching the compressing scheme based on the referred attribute.

Abstract: A computer-readable recording medium stores therein an information processing program executable by a computer, the information processing program includes: an instruction for obtaining a matrix to be subject to a calculation for a matrix vector multiplication; an instruction for generating a first matrix in a first format, the first matrix representing a first element group that includes non-zero elements among elements on a part of diagonals, among a main diagonal and sub-diagonals parallel to the main diagonal in the obtained matrix; and an instruction for generating a second matrix in a second format different from the first format, the second matrix representing a second element group that includes the non-zero elements, among the elements in at least a part of rows or columns that form the obtained matrix, other than the elements on the part of the diagonals.

Abstract: An information processing apparatus that performs deep learning using a neural network includes a memory, and an arithmetic processing device that performs a process for layers of the neural network in a predetermined direction. The process for the layers includes: pre-determining a decimal point position of a fixed-point number of an intermediate data obtained by an operation of each of the layers; performing the arithmetic operation for each layer with the pre-determined decimal point position to obtain the intermediate data and acquiring first statistical information of a distribution of bits of the intermediate data; determining a decimal point position of the intermediate data based on the statistical information; and performing the arithmetic operation for each layer with the determined decimal point position again when the difference of the determined decimal point position and the pre-determined decimal point position is greater than a threshold value.

Abstract: An arithmetic processing device that executes a single instruction/multiple data (SIMD) operation, includes a memory; and a processor coupled to the memory and configured to register an indefinite cycle instruction of a plurality of instructions to a first queue, register other instructions other than the indefinite cycle instruction of the plurality of instructions to a second queue, issue the indefinite cycle instruction registered to the first queue, and issue the other instructions registered to the second queue after issuing the indefinite cycle instruction.

Abstract: An information processor includes a memory; and a processor coupled to the memory and the processor configured to: acquire first statistical information about distribution of most significant bit position that is not a sign or least significant bit position that is not zero for each of a plurality of first fixed-point number data, the data being a computation result of the computation in the first layer; execute computation on a plurality of output data of the first layer according to a predetermined rule, in the computation in the second layer; and acquire second statistical information based on the predetermined rule and the first statistical information, and determine a bit range for limiting a bit width when a plurality of second fixed-point number data, the data being a computation result of the computation in the second layer, are stored in a register, based on the second statistical information.

Abstract: An information processing apparatus includes a processor including a first operation circuit that executes a product-sum operation, a second operation circuit that executes a certain operation, and a resister. The processor executes a first operation including the certain operation in a first layer in a neural network. The processor executes the first operation by a second method of calculating the certain operation by the second operation circuit, in a case where second operation time necessary for the first operation when the certain operation is executed by the second operation circuit is less than memory transfer time. Or the processor executes the first operation by a first method of calculating the certain operation by an approximate calculation by the first operation circuit, in a case where first operation time necessary for the first operation when executed by the first method is less than the memory transfer time.

Abstract: An arithmetic processing apparatus includes: a memory that stores, when a training of a given machine learning model is repeatedly performed in a plurality of iterations, an error of a decimal point position of each of a plurality of fixed-point number data obtained one in each of the plurality of iterations, the error being obtained based on statistical information related to a distribution of leftmost set bit positions for positive number and leftmost unset bit positions for negative number or a distribution of rightmost set bit positions of the plurality of fixed-point number data; and a processor coupled to the memory, the processor being configured to: determine, based on a tendency of the error in each of the plurality of iterations, an offset amount for correcting a decimal point position of fixed-point number data used in the training.

Abstract: An arithmetic processing device includes one or more memories; and one or more processors includes execute an operation of fixed-point number data, acquire statistical information that indicates a distribution of positions of most significant bits of a plurality of fixed-point number data obtained by the operation, update, based on the statistical information, a range for restriction of bit width of the plurality of fixed-point number data to be used for the operation, estimate respective data amount after compression of the plurality of fixed-point number data by a plurality of compression methods based on the statistical information, determine a compression method by which data amount after compression of the plurality of fixed-point number data is minimum among plurality of compression methods, transfer the plurality of fixed-point number data compressed by the compression method to the one or more memories.

Abstract: A compound represented by the following formula (1): wherein, R1 is a linear or branched alkyl group having 1 to 3 carbon atoms or a hydroxyl group; and R2 is a 1-pyrrolyl group, a 2-pyrrolyl group, or a 3-pyrrolyl group. The present invention can provide a means highly effective in contributing to savory roasting flavor and capable of imparting fragrance with natural feeling.

Abstract: An information processing device performing deep learning using a first number of processing devices that perform processes in parallel, the deep learning being performed using dynamic fixed-point number, the information processing device includes a processor. The processor configured to allocate, when allocating a propagation operation in a layer of the deep learning to the first number of processing devices, a second number of processing devices for every third number of pieces of input data, the third number being less than a first number, the second number of the processing device acquiring a statistical information used for adjusting decimal point positions of the dynamic fixed-point numbers, and allocate output channels for every third number of pieces of input data while shifting the output channels by a fourth number.

Abstract: An operation processing device includes: a memory; and a processor coupled to the memory and configured to: acquire statistical information on distribution of bits in fixed point number data after execution of an instruction on the fixed point number data; and update a decimal point position of the fixed point number data.

Abstract: An arithmetic processing device includes a memory and a processor coupled to the memory. The processor configured to calculate statistical information of a first operation result by executing the predetermined operation using input data as a first fixed-point number with a first decimal point at a first decimal point position, determine a second decimal point position using the statistical information, and calculate a second operation result when the predetermined operation is executed using the input data as a second fixed-point number with a second decimal point at the second decimal point position.

Abstract: An information processing apparatus includes a memory and a processor coupled to the memory. The processor acquires statistical information on a distribution of bits in floating point number data after executing an instruction on the floating point number data, and converts the floating point number data to fixed point number data.

Abstract: An operation processing apparatus includes a memory and a processor coupled to the memory. The processor executes an operation according to an operation instruction, acquires statistical information for a distribution of bits in fixed point data after an execution of an operation for the fixed point data according to an acquisition instruction, and outputs the statistical information to a register designated by the acquisition instruction.

Abstract: An arithmetic processing apparatus includes: a memory that stores, when a training of a given machine learning model is repeatedly performed in a plurality of iterations, an error of a decimal point position of each of a plurality of fixed-point number data obtained one in each of the plurality of iterations, the error being obtained baaed on statistical information related to a distribution of leftmost set bit positions for positive number and leftmost unset bit positions for negative number or a distribution of rightmost set bit positions of the plurality of fixed-point number data; and a processor coupled to the memory, the processor being configured to: determine, based on a tendency of the error in each of the plurality of iterations, an offset amount for correcting a decimal point position of fixed-point number data used in the training.

Abstract: An arithmetic processor includes a plurality of arithmetic circuits that individually execute an arithmetic operation for fixed point data; and at least one of first and second statistical information is acquired regarding a plurality of fixed point data that are results of arithmetic operation executed by the plurality of arithmetic circuits. The first statistical information is obtained by accumulating a bit pattern, which is obtained by setting a flag bit to each of bit positions corresponding to a range from a least-significant-bit position to a highest-order bit position for each of the digits corresponding to the bit positions, and the second statistical information is obtained by accumulating a bit pattern, which is obtained by setting a flag bit to each of bit positions corresponding to a range from the position of the sign bit to a lowest-order-bit position for each of the digits corresponding to the bit positions.

Abstract: An information processor includes a memory; and a processor coupled to the memory and the processor configured to: acquire first statistical information about distribution of most significant bit position that is not a sign or least significant bit position that is not zero for each of a plurality of first fixed-point number data, the data being a computation result of the computation in the first layer; execute computation on a plurality of output data of the first layer according to a predetermined rule, in the computation in the second layer; and acquire second statistical information based on the predetermined rule and the first statistical information, and determine a bit range for limiting a bit width when a plurality of second fixed-point number data, the data being a computation result of the computation in the second layer, are stored in a register, based on the second statistical information.

Abstract: A processor includes: a plurality of processor cores; and an internal memory configured to be accessed from the plurality of processor cores, wherein an arithmetic circuit provided in any of the plurality of processor cores includes: a plurality of first registers provided in a first stage of the arithmetic circuit, a regular addition circuit including a first adder and a second register, the first adder being configured to add a plurality of outputs of the plurality of first registers, the second register being configured to be provided in a second stage and latch an output of the first adder, an overtaking addition circuit including a second adder, the second adder being configured to add a plurality of outputs of the plurality of first registers, and a synthesis circuit including a third adder and a third register.

Abstract: An information processing apparatus includes a processor including a first operation circuit that executes a product-sum operation, a second operation circuit that executes a certain operation, and a resister. The processor executes a first operation including the certain operation in a first layer in a neural network. The processor executes the first operation by a second method of calculating the certain operation by the second operation circuit, in a case where second operation time necessary for the first operation when the certain operation is executed by the second operation circuit is less than memory transfer time. Or the processor executes the first operation by a first method of calculating the certain operation by an approximate calculation by the first operation circuit, in a case where first operation time necessary for the first operation when executed by the first method is less than the memory transfer time.