Abstract: A transmitter for transmitting payload data and emergency information using data symbols in a single-carrier or multi-carrier broadcast system comprises a modulator configured to modulate one or more transmission symbols with signaling data for use in detecting and recovering the payload data at a receiver and to modulate one or more transmission symbols with the payload data. An emergency information receiver receives emergency information carrying information of an actual emergency. An emergency information embedder embeds emergency information into one or more transmission symbols, wherein the emergency information is embedded within a predetermined time period after its reception by using a resource used for carrying signaling data and/or payload data if no emergency information shall be transmitted. A transmission unit transmits the transmission symbols.

Abstract: A transmitter for transmitting payload data and emergency information using data symbols in a single-carrier or multi-carrier broadcast system comprises a modulator configured to modulate one or more transmission symbols with signaling data for use in detecting and recovering the payload data at a receiver and to modulate one or more transmission symbols with the payload data. An emergency information receiver receives emergency information carrying information of an actual emergency. An emergency information embedder embeds emergency information into one or more transmission symbols, wherein the emergency information is embedded within a predetermined time period after its reception by using a resource used for carrying signaling data and/or payload data if no emergency information shall be transmitted. A transmission unit transmits the transmission symbols.

Abstract: A transmitter for transmitting payload data and emergency information using data symbols in a single-carrier or multi-carrier broadcast system includes a modulator configured to modulate one or more transmission symbols with signaling data for use in detecting and recovering the payload data at a receiver and to modulate one or more transmission symbols with the payload data. An emergency information receiver receives emergency information carrying information of an actual emergency. An emergency information embedder embeds emergency information into one or more transmission symbols, wherein the emergency information is embedded within a predetermined time period after its reception by using a resource used for carrying signaling data and/or payload data if no emergency information shall be transmitted. A transmission unit transmits the transmission symbols.

Abstract: A transmitter for transmitting payload data and emergency information using data symbols in a single-carrier or multi-carrier broadcast system includes a modulator configured to modulate one or more transmission symbols with signaling data for use in detecting and recovering the payload data at a receiver and to modulate one or more transmission symbols with the payload data. An emergency information receiver receives emergency information carrying information of an actual emergency. An emergency information embedder embeds emergency information into one or more transmission symbols, wherein the emergency information is embedded within a predetermined time period after its reception by using a resource used for carrying signaling data and/or payload data if no emergency information shall be transmitted. A transmission unit transmits the transmission symbols.

Abstract: A decoding apparatus and method is disclosed by which the decoder error occurrence probability is suppressed and a high decoding performance can be achieved. An ABP decoding apparatus diagonalizes a parity check matrix, updates LLR values, decodes the LLR values and then adds a decoded word obtained by the decoding to a decoded word list. The ABP decoding apparatus repeats the decoding procedure as inner repetitive decoding by a predetermined number of times. Further, as the ABP decoding apparatus successively changes initial values for priority ranks of the LLR values, it repeats the inner repetitive decoding as outer repetitive decoding by a predetermined number of times. Then, the ABP decoding apparatus selects an optimum one of the decoded words from within a decoded word list obtained by the repeated inner repetitive decoding. The invention is applied to an error correction system.

Abstract: The present invention relates to a decoding method and a decoder, a program, a recording-and-reproducing apparatus and a method, and a reproducing apparatus and a method that are suitable for decoding encoded data encoded by using a linear code on ring R. A low-density processing unit performs parity-check-matrix low-density processing, performs linear combination for rows of a parity check matrix included in an obtained reception word, and generates a parity check matrix according to the linear-combination result, thereby reducing the density of the parity check matrix used for decoding, at step S21. Then, at step S22, an LDPC decoding unit performs decoding by using a sum product algorithm (SPA) by using the parity check matrix whose density is reduced through the processing performed at step S21. Where the processing at step S22 is finished, the LDPC decoding unit finishes decoding for the reception word. The present invention can be used for an error-correction system.

Abstract: The present invention provides a decoding apparatus for carrying out a decoding process on a ring-R linear code. The decoding apparatus includes coded-word holding means for acquiring a coded word with a code length reduced by omission of some symbols from the coded word and for holding the coded word; known-information addition means for attaching a reliability level of each of the symbols omitted from the coded word to reduce its code length as known symbols each having a known value to the coded word held by the coded-word holding means as known information; and repetitive decoding means for repeatedly carrying out a decoding process using belief propagation on the coded word including the known information attached to the coded word by the known-information addition means.

Abstract: Disclosed is an apparatus for encoding data into linear codes on a ring R, including: as many shift registers as the length of information input thereto, the shift registers having a plurality of memory elements; a shift adding unit for adding values which are cyclically input depending on a check matrix for the linear codes, from the shift registers; a storage unit for storing parity values of the linear codes; and an accumulative adding unit for adding a sum from the shift adding unit and the parity values of the linear codes stored in the storage unit to each other to determine new parity values of the linear codes, and supplying the new parity values to the storage unit.

Abstract: The present invention relates to a decoding method and a decoding apparatus in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to a program therefor. By using a transformation check matrix obtained by performing one of or both a row permutation and a column permutation on an original check matrix of LDPC (Low Density Parity Check) codes, the LDPC codes are decoded. In this case, by using, as a formation matrix, a P×P unit matrix, a quasi-unit matrix in which one or more 1s, which are elements of the unit matrix, are substituted with 0, a shift matrix in which the unit matrix or the quasi-unit matrix is cyclically shifted, a sum matrix, which is the sum of two or more of the unit matrix, the quasi-unit matrix, and the shift matrix, and a P×P 0-matrix, the transformation check matrix is represented by a combination of a plurality of the formation matrices.

Abstract: The present invention provides a decoding apparatus for carrying out a decoding process on a ring-R linear code. The decoding apparatus includes coded-word holding means for acquiring a coded word with a code length reduced by omission of some symbols from the coded word and for holding the coded word; known-information addition means for attaching a reliability level of each of the symbols omitted from the coded word to reduce its code length as known symbols each having a known value to the coded word held by the coded-word holding means as known information; and repetitive decoding means for repeatedly carrying out a decoding process using belief propagation on the coded word including the known information attached to the coded word by the known-information addition means.

Abstract: A decoding apparatus and method is disclosed by which the decoder error occurrence probability is suppressed and a high decoding performance can be achieved. An ABP decoding apparatus diagonalizes a parity check matrix, updates LLR values, decodes the LLR values and then adds a decoded word obtained by the decoding to a decoded word list. The ABP decoding apparatus repeats the decoding procedure as inner repetitive decoding by a predetermined number of times. Further, as the ABP decoding apparatus successively changes initial values for priority ranks of the LLR values, it repeats the inner repetitive decoding as outer repetitive decoding by a predetermined number of times. Then, the ABP decoding apparatus selects an optimum one of the decoded words from within a decoded word list obtained by the repeated inner repetitive decoding. The invention is applied to an error correction system.

Abstract: A circuit design method able to design a processing circuit to be small in scale when designing a processing circuit for performing a plurality of different processings on predetermined data, comprising a first step of identifying second processings performing the same processing on the same data among pluralities of second processings forming each of a plurality of first processings when designing a processing circuit for applying a plurality of different first processings on predetermined data and a second step of designing a processing circuit having a processing circuit shared by the plurality of first processings and for performing the second processings identified at the first step.

Abstract: A circuit design method able to design a processing circuit for processing a finite field with fewer circuit design elements and in a smaller-size than the past comprising obtaining a first primitive root ?1 on the basis of a first polynomial for a first extension from a first finite field to a second finite field, obtaining a second primitive root ?2 on the basis of a second polynomial for a second extension from the second finite field to a third finite field, wherein a coefficient of a 0-th term is defined using the first primitive root ?1 obtained above and the coefficient of the 0-th term of the first polynomial, defining processing on the third finite field using a base expressed using the second primitive root ?2, and designing the processing circuit for performing that processing.

Abstract: The present invention relates to a decoding method and a decoder, a program, a recording-and-reproducing apparatus and a method, and a reproducing apparatus and a method that are suitable for decoding encoded data encoded by using a linear code on ring R. A low-density processing unit performs parity-check-matrix low-density processing, performs linear combination for rows of a parity check matrix included in an obtained reception word, and generates a parity check matrix according to the linear-combination result, thereby reducing the density of the parity check matrix used for decoding, at step S21. Then, at step S22, an LDPC decoding unit performs decoding by using a sum product algorithm (SPA) by using the parity check matrix whose density is reduced through the processing performed at step S21. Where the processing at step S22 is finished, the LDPC decoding unit finishes decoding for the reception word. The present invention can be used for an error-correction system.

Abstract: The present invention relates to a decoding method and a decoding apparatus in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to a program therefor. By using a transformation check matrix obtained by performing one of or both a row permutation and a column permutation on an original check matrix of LDPC (Low Density Parity Check) codes, the LDPC codes are decoded. In this case, by using, as a formation matrix, a P×P unit matrix, a quasi-unit matrix in which one or more is, which are elements of the unit matrix, are substituted with 0, a shift matrix in which the unit matrix or the quasi-unit matrix is cyclically shifted, a sum matrix, which is the sum of two or more of the unit matrix, the quasi-unit matrix, and the shift matrix, and a P×P 0-matrix, the transformation check matrix is represented by a combination of a plurality of the formation matrices.

Abstract: Disclosed is an apparatus for encoding data into linear codes on a ring R, including: as many shift registers as the length of information input thereto, the shift registers having a plurality of memory elements; a shift adding unit for adding values which are cyclically input depending on a check matrix for the linear codes, from the shift registers; a storage unit for storing parity values of the linear codes; and an accumulative adding unit for adding a sum from the shift adding unit and the parity values of the linear codes stored in the storage unit to each other to determine new parity values of the linear codes, and supplying the new parity values to the storage unit.

Abstract: A circuit design method able to design a processing circuit to be small in scale when designing a processing circuit for performing a plurality of different processings on predetermined data, comprising a first step of identifying second processings performing the same processing on the same data among pluralities of second processings forming each of a plurality of first processings when designing a processing circuit for applying a plurality of different first processings on predetermined data and a second step of designing a processing circuit having a processing circuit shared by the plurality of first processings and for performing the second processings identified at the first step.

Abstract: A circuit design method able to design a processing circuit for processing a finite field with fewer circuit design elements and in a smaller-size than the past comprising obtaining a first primitive root &agr;1 on the basis of a first polynomial for a first extension from a first finite field to a second finite field, obtaining a second primitive root &agr;2 on the basis of a second polynomial for a second extension from the second finite field to a third finite field, wherein a coefficient of a 0-th term is defined using the first primitive root &agr;1 obtained above and the coefficient of the 0-th term of the first polynomial, defining processing on the third finite field using a base expressed using the second primitive root &agr;2, and designing the processing circuit for performing that processing.