Patents by Inventor Makiko Naemura

Makiko Naemura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11104165
    Abstract: Previously, a customer may not have known which information was acquired and may have felt anxiety. In addition, only internal data of the apparatus was previously acquired. However, in order to determine a trouble in the inkjet printer with high precision, visual information such as a state of a printer mechanism or a conveyance line and a print result is also necessary to determine the apparatus state. Therefore, it is necessary to establish a maintenance system capable of acquiring such information.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: August 31, 2021
    Assignee: Hitachi Industrial Equipment Systems Co., Ltd.
    Inventors: Hiroko Kurihara, Takashi Kawano, Nobuhiro Harada, Kenjiro Fujii, Tomohisa Kohiyama, Makiko Naemura
  • Publication number: 20200298601
    Abstract: Previously, a customer may not have known which information was acquired and may have felt anxiety. In addition, only internal data of the apparatus was previously acquired. However, in order to determine a trouble in the inkjet printer with high precision, visual information such as a state of a printer mechanism or a conveyance line and a print result is also necessary to determine the apparatus state. Therefore, it is necessary to establish a maintenance system capable of acquiring such information.
    Type: Application
    Filed: March 29, 2016
    Publication date: September 24, 2020
    Inventors: Hiroko KURIHARA, Takashi KAWANO, Nobuhiro HARADA, Kenjiro FUJII, Tomohisa KOHIYAMA, Makiko NAEMURA
  • Patent number: 7861115
    Abstract: To reset only the CPU in a component in an abnormal condition without affecting CPUs of components in a normal condition, a multi-component system, in which a plurality of components each including at least a CPU are connected via a common bus to each other, includes a first reset signal generating unit which generates a reset signal by a switch operation to send the reset signal to respective components and a judge unit which is disposed in each component to determine whether or not resetting of a CPU is allowed. The judge unit inhibits, if the CPU is in a normal condition, the resetting of the CPU in response to the reset signal and resets, if the CPU is in an abnormal condition, the CPU in response to the reset signal.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: December 28, 2010
    Assignee: Hitachi Industrial Equipment Systems Co., Ltd.
    Inventors: Norihisa Yanagihara, Hajime Kihara, Tsutomu Yamada, Makiko Naemura, Kenji Seino
  • Patent number: 7814224
    Abstract: An information processor disclosed herein prevents adverse impacts on higher priority processing due to extremely frequent receive processing when inbound traffic from a network is over-traffic state (under a DoS attack). The information processor attached to a network collects information about traffic state and, if it is determined that over-traffic state is present, deactivates the communication processing function without passing an interrupt request due to communication to the data processing block. In this state, the information processor continues to collect information about traffic state and, when it is determined that over-traffic state has terminated, starts to transfer an interrupt request to the data processing block and makes the communication processing function recover.
    Type: Grant
    Filed: January 24, 2008
    Date of Patent: October 12, 2010
    Assignee: Hitachi Industrial Equipment Systems Co.
    Inventors: Tatsuya Maruyama, Tsutomu Yamada, Hideaki Suzuki, Norihisa Yanagihara, Makiko Naemura
  • Patent number: 7716405
    Abstract: A computer system, being a stack bus system in which a plurality of computer modules are stacked and connected to one another and being capable of automatically matching and allocating bus resources such as clocks and interrupts, is provided. In the computer system including one system module and n peripheral modules, each peripheral module includes an interrupt selector, a clock selector, an arbitration signal selector, a resource decision unit, and a position identification unit. The position identification unit cooperates with a position configuration unit present in the system module to identify a position of the module, which includes the position identification unit, in the computer system, and autonomously decides bus resources used by the module. By allowing the interrupt selector, the clock selector, and the arbitration signal selector to select and use the decided bus resources, each peripheral module can match and configure the bus resources in the computer system.
    Type: Grant
    Filed: November 15, 2006
    Date of Patent: May 11, 2010
    Assignee: Hitachi Industrial Equipment Systems Co., Ltd.
    Inventors: Tsutomu Yamada, Hiromichi Endoh, Noritaka Matsumoto, Satoru Funaki, Tatsuya Maruyama, Atsushi Ito, Fumiyuki Tamura, Norihisa Yanagihara, Makiko Naemura
  • Publication number: 20090013221
    Abstract: To reset only the CPU in a component in an abnormal condition without affecting CPUs of components in a normal condition, a multi-component system, in which a plurality of components each including at least a CPU are connected via a common bus to each other, includes a first reset signal generating unit which generates a reset signal by a switch operation to send the reset signal to respective components and a judge unit which is disposed in each component to determine whether or not resetting of a CPU is allowed. The judge unit inhibits, if the CPU is in a normal condition, the resetting of the CPU in response to the reset signal and resets, if the CPU is in an abnormal condition, the CPU in response to the reset signal.
    Type: Application
    Filed: June 24, 2008
    Publication date: January 8, 2009
    Applicant: Hitachi Industrial Equipment System Co., Ltd.
    Inventors: Norihisa Yanagihara, Hajime Kihara, Tsutomu Yamada, Makiko Naemura, Kenji Seino
  • Publication number: 20080195732
    Abstract: An information processor disclosed herein prevents adverse impacts on higher priority processing due to extremely frequent receive processing when inbound traffic from a network is over-traffic state (under a DoS attack). The information processor attached to a network collects information about traffic state and, if it is determined that over-traffic state is present, deactivates the communication processing function without passing an interrupt request due to communication to the data processing block. In this state, the information processor continues to collect information about traffic state and, when it is determined that over-traffic state has terminated, starts to transfer an interrupt request to the data processing block and makes the communication processing function recover.
    Type: Application
    Filed: January 24, 2008
    Publication date: August 14, 2008
    Inventors: Tatsuya Maruyama, Tsutomu Yamada, Hideaki Suzuki, Norihisa Yanagihara, Makiko Naemura
  • Publication number: 20070112983
    Abstract: A computer system, being a stack bus system in which a plurality of computer modules are stacked and connected to one another and being capable of automatically matching and allocating bus resources such as clocks and interrupts, is provided. In the computer system including one system module and n peripheral modules, each peripheral module includes an interrupt selector, a clock selector, an arbitration signal selector, a resource decision unit, and a position identification unit. The position identification unit cooperates with a position configuration unit present in the system module to identify a position of the module, which includes the position identification unit, in the computer system, and autonomously decides bus resources used by the module. By allowing the interrupt selector, the clock selector, and the arbitration signal selector to select and use the decided bus resources, each peripheral module can match and configure the bus resources in the computer system.
    Type: Application
    Filed: November 15, 2006
    Publication date: May 17, 2007
    Inventors: Tsutomu Yamada, Hiromichi Endoh, Noritaka Matsumoto, Satoru Funaki, Tatsuya Maruyama, Atsushi Ito, Fumiyuki Tamura, Norihisa Yanagihara, Makiko Naemura
  • Publication number: 20030212567
    Abstract: A plurality of vehicles with cameras and other sensors collect images, including other data as a normal event, or upon demand in an emergency, or when requested to do so by another vehicle, an occupant or a service center. Images may be permanently stored in the vehicles and indexed in a directory at the service center so that the images may selectively sent to the service center or another vehicle without consuming storage space at the service center. Upon the occurrence of an emergency event, an emergency signal is broadcast to vehicles within the area to save and transmit an immediate past image history and an immediate future image history.
    Type: Application
    Filed: May 7, 2002
    Publication date: November 13, 2003
    Applicant: Hitachi Ltd.
    Inventors: Yoichi Shintani, Tomohisa Kohiyama, Makiko Naemura