Patents by Inventor Makiko Naemura
Makiko Naemura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11104165Abstract: Previously, a customer may not have known which information was acquired and may have felt anxiety. In addition, only internal data of the apparatus was previously acquired. However, in order to determine a trouble in the inkjet printer with high precision, visual information such as a state of a printer mechanism or a conveyance line and a print result is also necessary to determine the apparatus state. Therefore, it is necessary to establish a maintenance system capable of acquiring such information.Type: GrantFiled: March 29, 2016Date of Patent: August 31, 2021Assignee: Hitachi Industrial Equipment Systems Co., Ltd.Inventors: Hiroko Kurihara, Takashi Kawano, Nobuhiro Harada, Kenjiro Fujii, Tomohisa Kohiyama, Makiko Naemura
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Publication number: 20200298601Abstract: Previously, a customer may not have known which information was acquired and may have felt anxiety. In addition, only internal data of the apparatus was previously acquired. However, in order to determine a trouble in the inkjet printer with high precision, visual information such as a state of a printer mechanism or a conveyance line and a print result is also necessary to determine the apparatus state. Therefore, it is necessary to establish a maintenance system capable of acquiring such information.Type: ApplicationFiled: March 29, 2016Publication date: September 24, 2020Inventors: Hiroko KURIHARA, Takashi KAWANO, Nobuhiro HARADA, Kenjiro FUJII, Tomohisa KOHIYAMA, Makiko NAEMURA
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Patent number: 7861115Abstract: To reset only the CPU in a component in an abnormal condition without affecting CPUs of components in a normal condition, a multi-component system, in which a plurality of components each including at least a CPU are connected via a common bus to each other, includes a first reset signal generating unit which generates a reset signal by a switch operation to send the reset signal to respective components and a judge unit which is disposed in each component to determine whether or not resetting of a CPU is allowed. The judge unit inhibits, if the CPU is in a normal condition, the resetting of the CPU in response to the reset signal and resets, if the CPU is in an abnormal condition, the CPU in response to the reset signal.Type: GrantFiled: June 24, 2008Date of Patent: December 28, 2010Assignee: Hitachi Industrial Equipment Systems Co., Ltd.Inventors: Norihisa Yanagihara, Hajime Kihara, Tsutomu Yamada, Makiko Naemura, Kenji Seino
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Patent number: 7814224Abstract: An information processor disclosed herein prevents adverse impacts on higher priority processing due to extremely frequent receive processing when inbound traffic from a network is over-traffic state (under a DoS attack). The information processor attached to a network collects information about traffic state and, if it is determined that over-traffic state is present, deactivates the communication processing function without passing an interrupt request due to communication to the data processing block. In this state, the information processor continues to collect information about traffic state and, when it is determined that over-traffic state has terminated, starts to transfer an interrupt request to the data processing block and makes the communication processing function recover.Type: GrantFiled: January 24, 2008Date of Patent: October 12, 2010Assignee: Hitachi Industrial Equipment Systems Co.Inventors: Tatsuya Maruyama, Tsutomu Yamada, Hideaki Suzuki, Norihisa Yanagihara, Makiko Naemura
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Patent number: 7716405Abstract: A computer system, being a stack bus system in which a plurality of computer modules are stacked and connected to one another and being capable of automatically matching and allocating bus resources such as clocks and interrupts, is provided. In the computer system including one system module and n peripheral modules, each peripheral module includes an interrupt selector, a clock selector, an arbitration signal selector, a resource decision unit, and a position identification unit. The position identification unit cooperates with a position configuration unit present in the system module to identify a position of the module, which includes the position identification unit, in the computer system, and autonomously decides bus resources used by the module. By allowing the interrupt selector, the clock selector, and the arbitration signal selector to select and use the decided bus resources, each peripheral module can match and configure the bus resources in the computer system.Type: GrantFiled: November 15, 2006Date of Patent: May 11, 2010Assignee: Hitachi Industrial Equipment Systems Co., Ltd.Inventors: Tsutomu Yamada, Hiromichi Endoh, Noritaka Matsumoto, Satoru Funaki, Tatsuya Maruyama, Atsushi Ito, Fumiyuki Tamura, Norihisa Yanagihara, Makiko Naemura
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Publication number: 20090013221Abstract: To reset only the CPU in a component in an abnormal condition without affecting CPUs of components in a normal condition, a multi-component system, in which a plurality of components each including at least a CPU are connected via a common bus to each other, includes a first reset signal generating unit which generates a reset signal by a switch operation to send the reset signal to respective components and a judge unit which is disposed in each component to determine whether or not resetting of a CPU is allowed. The judge unit inhibits, if the CPU is in a normal condition, the resetting of the CPU in response to the reset signal and resets, if the CPU is in an abnormal condition, the CPU in response to the reset signal.Type: ApplicationFiled: June 24, 2008Publication date: January 8, 2009Applicant: Hitachi Industrial Equipment System Co., Ltd.Inventors: Norihisa Yanagihara, Hajime Kihara, Tsutomu Yamada, Makiko Naemura, Kenji Seino
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Publication number: 20080195732Abstract: An information processor disclosed herein prevents adverse impacts on higher priority processing due to extremely frequent receive processing when inbound traffic from a network is over-traffic state (under a DoS attack). The information processor attached to a network collects information about traffic state and, if it is determined that over-traffic state is present, deactivates the communication processing function without passing an interrupt request due to communication to the data processing block. In this state, the information processor continues to collect information about traffic state and, when it is determined that over-traffic state has terminated, starts to transfer an interrupt request to the data processing block and makes the communication processing function recover.Type: ApplicationFiled: January 24, 2008Publication date: August 14, 2008Inventors: Tatsuya Maruyama, Tsutomu Yamada, Hideaki Suzuki, Norihisa Yanagihara, Makiko Naemura
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Publication number: 20070112983Abstract: A computer system, being a stack bus system in which a plurality of computer modules are stacked and connected to one another and being capable of automatically matching and allocating bus resources such as clocks and interrupts, is provided. In the computer system including one system module and n peripheral modules, each peripheral module includes an interrupt selector, a clock selector, an arbitration signal selector, a resource decision unit, and a position identification unit. The position identification unit cooperates with a position configuration unit present in the system module to identify a position of the module, which includes the position identification unit, in the computer system, and autonomously decides bus resources used by the module. By allowing the interrupt selector, the clock selector, and the arbitration signal selector to select and use the decided bus resources, each peripheral module can match and configure the bus resources in the computer system.Type: ApplicationFiled: November 15, 2006Publication date: May 17, 2007Inventors: Tsutomu Yamada, Hiromichi Endoh, Noritaka Matsumoto, Satoru Funaki, Tatsuya Maruyama, Atsushi Ito, Fumiyuki Tamura, Norihisa Yanagihara, Makiko Naemura
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Publication number: 20030212567Abstract: A plurality of vehicles with cameras and other sensors collect images, including other data as a normal event, or upon demand in an emergency, or when requested to do so by another vehicle, an occupant or a service center. Images may be permanently stored in the vehicles and indexed in a directory at the service center so that the images may selectively sent to the service center or another vehicle without consuming storage space at the service center. Upon the occurrence of an emergency event, an emergency signal is broadcast to vehicles within the area to save and transmit an immediate past image history and an immediate future image history.Type: ApplicationFiled: May 7, 2002Publication date: November 13, 2003Applicant: Hitachi Ltd.Inventors: Yoichi Shintani, Tomohisa Kohiyama, Makiko Naemura