Patents by Inventor Makiko Shinohara
Makiko Shinohara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8464258Abstract: When the number of logical CPUs increases as the number of LPARs increases, a physical CPU amount which a hypervisor uses will increase and thus the physical CPU resource cannot be effectively utilized. Grouping of LPARs and physical CPUs is performed and a logical CPU to which a physical CPU is allocated is selected from logical CPUs of an LPAR within a group.Type: GrantFiled: April 26, 2011Date of Patent: June 11, 2013Assignee: Hitachi, Ltd.Inventors: Makiko Shinohara, Shuhei Matsumoto, Hironori Inoue
-
Patent number: 8443364Abstract: A user interface function for a virtual machine system based on a server or a PC is provided only by applying software without using SVP or the like. A control virtual machine is provided for controlling a virtual machine control screen which is displayed for defining virtual machines and instructing operations to the virtual machines. A virtual machine control program exclusively displays either a screen for each virtual machine or the virtual machine control screen in response to a screen switching instruction from an input device.Type: GrantFiled: March 29, 2010Date of Patent: May 14, 2013Assignee: Hitachi, Ltd.Inventors: Toyohisa Imada, Takashi Shimojo, Makiko Shinohara, Yoshihiro Harima
-
Publication number: 20110302579Abstract: When the number of logical CPUs increases as the number of LPARs increases, a physical CPU amount which a hypervisor uses will increase and thus the physical CPU resource cannot be effectively utilized. Grouping of LPARs and physical CPUs is performed and a logical CPU to which a physical CPU is allocated is selected from logical CPUs of an LPAR within a group.Type: ApplicationFiled: April 26, 2011Publication date: December 8, 2011Inventors: Makiko Shinohara, Shuhei Matsumoto, Hironori Inoue
-
Publication number: 20100186012Abstract: A user interface function for a virtual machine system based on a server or a PC is provided only by applying software without using SVP or the like. A control virtual machine is provided for controlling a virtual machine control screen which is displayed for defining virtual machines and instructing operations to the virtual machines. A virtual machine control program exclusively displays either a screen for each virtual machine or the virtual machine control screen in response to a screen switching instruction from an input device.Type: ApplicationFiled: March 29, 2010Publication date: July 22, 2010Applicant: Hitachi, LTD.Inventors: Toyohisa Imada, Takashi Shimojo, Makiko Shinohara, Yoshihiro Harima
-
Patent number: 7721285Abstract: A user interface function for a virtual machine system based on a server or a PC is provided only by applying software without using SVP or the like. A control virtual machine is provided for controlling a virtual machine control screen which is displayed for defining virtual machines and instructing operations to the virtual machines. A virtual machine control program exclusively displays either a screen for each virtual machine or the virtual machine control screen in response to a screen switching instruction from an input device.Type: GrantFiled: February 12, 2007Date of Patent: May 18, 2010Assignee: Hitachi, Ltd.Inventors: Toyohisa Imada, Takashi Shimojo, Makiko Shinohara, Yoshihiro Harima
-
Publication number: 20090158004Abstract: A TLB virtualization method of a machine virtualization device which, in the case where a TLB is shadowed in a virtualization environment, avoids TLB entry conflicts and is capable of improving the performance of a virtualization environment; wherein a hypervisor is executed on a real machine, an OS is operated on a plurality of virtual machines generated by means of processing based on the hypervisor, TLB entry calculations are carried out using RID values in the virtual machines by means of hypervisor processing, the RID values in the virtual machines used in the TLB entry calculations in the real machine are translated into different values in said plurality of virtual machines, and, further, the values of the bit strings of translated RID values are modified.Type: ApplicationFiled: November 26, 2008Publication date: June 18, 2009Inventors: Tomohide Hasegawa, Makiko Shinohara, Norimitsu Hayakawa, Souichi Takashige
-
Patent number: 7509475Abstract: A virtual machine control method and a virtual machine system are disclosed. In the case where a guest program can be operated in a plurality of address translation modes and the same guest virtual address is translated into different host real addresses in each address translation mode, the illegal access to a host real address by illegal address translation by double registration in the same page table is avoided, and the address translation mechanism is efficiently operated. A plurality of host page tables are prepared in the main storage, and one of the host page tables is selected with the change in address translation mode of the guest program. The bottom address of the selected host page table is set in the host page table register thereby to switch the host page table.Type: GrantFiled: October 26, 2006Date of Patent: March 24, 2009Assignee: Hitachi, Ltd.Inventors: Makiko Shinohara, Akiko Mori, Shuhei Matsumoto, Isao Watanabe, Hiroyuki Mitome
-
Publication number: 20080184227Abstract: In a processor capping method in a virtual machine system, a complement virtual machine is created having a possessive processor time equal to the difference of subtraction of a possessive processor time given to the processor capping enabled virtual machine from a possessive processor time of the whole physical computer; a processor time by which each virtual machine utilizes the physical processor per unit time is determined; schedule priorities of each virtual machine and of the complement virtual machine are determined on the basis of their possessive processor times and the determined utilization processor time as well; and the schedule priority of the processor capping enabled virtual machine is compared with that of the complement virtual machine corresponding to the processor capping enabled computer to decide whether the schedule for the physical processor of the virtual processor the processor capping enabled virtual machine has is permissible or prohibitive.Type: ApplicationFiled: January 29, 2008Publication date: July 31, 2008Inventors: Shuhei MATSUMOTO, Hironori Inoue, Makiko Shinohara, Norimitsu Hayakawa
-
Patent number: 7272799Abstract: A user interface function for a virtual machine system based on a server or a PC is provided only by applying software without using SVP or the like. A control virtual machine is provided for controlling a virtual machine control screen which is displayed for defining virtual machines and instructing operations to the virtual machines. A virtual machine control program exclusively displays either a screen for each virtual machine or the virtual machine control screen in response to a screen switching instruction from an input device.Type: GrantFiled: April 18, 2002Date of Patent: September 18, 2007Assignee: Hitachi, Ltd.Inventors: Toyohisa Imada, Takashi Shimojo, Makiko Shinohara, Yoshihiro Harima
-
Publication number: 20070143754Abstract: A user interface function for a virtual machine system based on a server or a PC is provided only by applying software without using SVP or the like. A control virtual machine is provided for controlling a virtual machine control screen which is displayed for defining virtual machines and instructing operations to the virtual machines. A virtual machine control program exclusively displays either a screen for each virtual machine or the virtual machine control screen in response to a screen switching instruction from an input device.Type: ApplicationFiled: February 12, 2007Publication date: June 21, 2007Applicant: Hitachi, Ltd.Inventors: Toyohisa Imada, Takashi Shimojo, Makiko Shinohara, Yoshihiro Harima
-
Publication number: 20070101099Abstract: A virtual machine control method and a virtual machine system are disclosed. In the case where a guest program can be operated in a plurality of address translation modes and the same guest virtual address is translated into different host real addresses in each address translation mode, the illegal access to a host real address by illegal address translation by double registration in the same page table is avoided, and the address translation mechanism is efficiently operated. A plurality of host page tables are prepared in the main storage, and one of the host page tables is selected with the change in address translation mode of the guest program. The bottom address of the selected host page table is set in the host page table register thereby to switch the host page table.Type: ApplicationFiled: October 26, 2006Publication date: May 3, 2007Inventors: Makiko Shinohara, Akiko Mori, Shuhei Matsumoto, Isao Watanabe, Hiroyuki Mitome
-
Patent number: 6557166Abstract: Correction of a program which resides on a main storage and which is simultaneously callable by a plurality of command processors is performed by minimizing the stop time of a computer system without reloading a program. A particular command processor calls a correction execution program which corrects a program in accordance with a program correction command. The correction execution program reads program correction information, sets correction execution declaration information in all entries of other command processor in the correction execution declaration area of the main storage and after clearing all entries, the correction execution program corrects the program in accordance with the program correction information. The correction execution program sets correction completion reporting information in all entries for all of the other command processors in the correction completion reporting area of the main storage.Type: GrantFiled: December 29, 2000Date of Patent: April 29, 2003Assignee: Hitachi, Ltd.Inventors: Makiko Shinohara, Hideaki Amano
-
Publication number: 20020173863Abstract: A user interface function for a virtual machine system based on a server or a PC is provided only by applying software without using SVP or the like. A control virtual machine is provided for controlling a virtual machine control screen which is displayed for defining virtual machines and instructing operations to the virtual machines. A virtual machine control program exclusively displays either a screen for each virtual machine or the virtual machine control screen in response to a screen switching instruction from an input device.Type: ApplicationFiled: April 18, 2002Publication date: November 21, 2002Inventors: Toyohisa Imada, Takashi Shimojo, Makiko Shinohara, Yoshihiro Harima
-
Publication number: 20010000825Abstract: Correction of a program which resides on a main storage and which is simultaneously callable by a plurality of command processors is performed by minimizing the stop time of a computer system without reloading a program. A particular command processor calls a correction execution program which corrects a program in accordance with a program correction command. The correction execution program reads program correction information, sets correction execution declaration information in all entries of other command processor in the correction execution declaration area of the main storage and after clearing all entries, the correction execution program corrects the program in accordance with the program correction information. The correction execution program sets correction completion reporting information in all entries for all of the other command processors in the correction completion reporting area of the main storage.Type: ApplicationFiled: December 29, 2000Publication date: May 3, 2001Inventors: Makiko Shinohara, Hideaki Amano
-
Patent number: 6205577Abstract: Correction of a program which resides on a main storage and which is simultaneously callable by a plurality of command processors is performed by minimizing the stop time of a computer system without reloading a program. A particular command processor calls a correction execution program which corrects a program in accordance with a program correction command. The correction execution program reads program correction information, sets correction execution declaration information in all entries of other command processor in the correction execution declaration area of the main storage and after clearing all entries, the correction execution program corrects the program in accordance with the program correction information. The correction execution program sets correction completion reporting information in all entries for all of the other command processors in the correction completion reporting area of the main storage.Type: GrantFiled: March 8, 1996Date of Patent: March 20, 2001Assignee: Hitachi, Ltd.Inventors: Makiko Shinohara, Hideaki Amano
-
Patent number: 5996026Abstract: A connection method of a plurality of input/output channels between a plurality of sub-channels of an information processing system having a virtual machine running on a physical machine under control of a hypervisor and a plurality of devices. The method includes issuing from the hypervisor a command for setting configuration information defining a plurality of configuration structures between the sub-channels set for the respective virtual machines and the devices in a storage device and acquiring configuration information containing the sub-channel corresponding to a designated device from the configuration information corresponding to one of the virtual machines based on the device designation contained in the input/output command from the one virtual machine. The virtual machines are enabled after the issuance of the set command and before the issuance of the input/output command.Type: GrantFiled: April 4, 1997Date of Patent: November 30, 1999Assignee: Hitachi, Ltd.Inventors: Osamu Onodera, Makiko Shinohara, Kiichi Sato
-
Patent number: RE49925Abstract: The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rate r is 6/15, 8/15, or 10/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code.Type: GrantFiled: August 27, 2020Date of Patent: April 16, 2024Assignee: Saturn Licensing LLCInventors: Ryoji Ikegaya, Makiko Yamamoto, Yuji Shinohara