Patents by Inventor Makio Iida
Makio Iida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10650710Abstract: To provide a display body device and a display apparatus that allow for improvement of an electrostatic withstanding voltage, a display body device 10E includes: a wiring substrate 30; a light-emitting element 12 and a drive IC 13 that are disposed on the wiring substrate 30; and a wiring pattern 36 that is disposed on an outermost side, and is at least partially exposed and has a potential equal to a ground of each of the light-emitting element 12 and the drive IC 13.Type: GrantFiled: January 30, 2017Date of Patent: May 12, 2020Assignee: SONY CORPORATIONInventors: Akiyoshi Aoyagi, Makio Iida, Norifumi Hoshino
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Publication number: 20190019436Abstract: To provide a display body device and a display apparatus that allow for improvement of an electrostatic withstanding voltage, a display body device 10E includes: a wiring substrate 30; a light-emitting element 12 and a drive IC 13 that are disposed on the wiring substrate 30; and a wiring pattern 36 that is disposed on an outermost side, and is at least partially exposed and has a potential equal to a ground of each of the light-emitting element 12 and the drive IC 13.Type: ApplicationFiled: January 30, 2017Publication date: January 17, 2019Inventors: AKIYOSHI AOYAGI, MAKIO IIDA, NORIFUMI HOSHINO
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Patent number: 8063863Abstract: A picture display apparatus exploiting a liquid crystal display is disclosed. This picture display apparatus (10) includes an interpolator (11), an over-drive unit (12), an angle of visibility improvement unit (13), and a source driver (15) for driving a liquid crystal display panel (16). The interpolator converts the picture rate upwardly. The angle of visibility improvement unit (13) converts an input picture signal into a picture signal representing a grayscale level of the input picture signal by synthesis of liquid crystal transmittances of a plural number of temporally consecutive fields. Specifically, the angle of visibility improvement unit converts the input picture signal to a picture signal made up of a first field set to a signal value related with a high grayscale level and a second field set to a signal value related with a low grayscale level.Type: GrantFiled: June 15, 2006Date of Patent: November 22, 2011Assignee: Sony CorporationInventors: Tomoya Yano, Makio Iida, Yoshiki Shirochi
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Patent number: 7586272Abstract: A cold cathode fluorescent lamp apparatus has a cold cathode fluorescent lamp which can be lit readily and in which leak current is minimized. A pair of internal electrodes are disposed on an inner surface of the cold cathode fluorescent lamp, and a pair of external electrodes are provided on an outer surface of the cold cathode fluorescent lamp. The internal electrodes are driven by a dc driving circuit, and the current flow between the internal electrodes is controlled by a constant current circuit. The external electrodes are driven by an ac driving circuit.Type: GrantFiled: June 7, 2006Date of Patent: September 8, 2009Assignee: Sony CorporationInventors: Makio Iida, Norimasa Furukawa
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Publication number: 20080284699Abstract: A picture display apparatus exploiting a liquid crystal display is disclosed. This picture display apparatus (10) includes an interpolator (11), an over-drive unit (12), an angle of visibility improvement unit (13), and a source driver (15) for driving a liquid crystal display panel (16). The interpolator converts the picture rate upwardly. The angle of visibility improvement unit (13) converts an input picture signal into a picture signal representing a grayscale level of the input picture signal by synthesis of liquid crystal transmittances of a plural number of temporally consecutive fields. Specifically, the angle of visibility improvement unit converts the input picture signal to a picture signal made up of a first field set to a signal value related with a high grayscale level and a second field set to a signal value related with a low grayscale level.Type: ApplicationFiled: June 15, 2006Publication date: November 20, 2008Applicant: Sony CorporationInventors: Tomoya Yano, Makio Iida, Yoshiki Shirochi
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Publication number: 20080272998Abstract: An image display device and an image display method able to display a middle gray-scale by using a plurality of pixels or fields and, at the same time, improve viewing angle characteristics are provided. When displaying an image via a direct view type liquid crystal display screen, a gray-scales of an input video signal is converted to characteristic values (transmittances) of pixels two-dimensionally arranged with respect to the display image, and the gray-scale is converted so as to include, among a plurality of pixels or fields expressing a middle gray-scale, at least one pixel or field converted to a first characteristic value obtained by adding a positive correction value to the gray-scale of the input video signal, and at least one pixel or field converted to a second characteristic value obtained by adding a negative correction value to the gray-scale of the input video signal.Type: ApplicationFiled: July 15, 2005Publication date: November 6, 2008Inventors: Tomoya Yano, Yoshiki Shirochi, Toshinobu Isobe, Makio Iida
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Publication number: 20060284565Abstract: A cold cathode fluorescent lamp apparatus has a cold cathode fluorescent lamp which can be lit readily and in which leak current is minimized. A pair of internal electrodes are disposed on an inner surface of the cold cathode fluorescent lamp, and a pair of external electrodes are provided on an outer surface of the cold cathode fluorescent lamp. The internal electrodes are driven by a dc driving circuit, and the current flow between the internal electrodes is controlled by a constant current circuit. The external electrodes are driven by an ac driving circuit.Type: ApplicationFiled: June 7, 2006Publication date: December 21, 2006Applicant: Sony CorporationInventors: Makio Iida, Norimasa Furukawa
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Patent number: 6831331Abstract: A semiconductor device is provided having a power transistor structure. The power transistor structure includes a plurality of first wells disposed independently at a surface portion of a semiconductor layer; a deep region having a portion disposed in the semiconductor layer between the first wells; a drain electrode connected to respective drain regions in the first wells; a source electrode connected to respective source regions and channel well regions in the first wells, such that either the drain electrode or the source electrode is connected to an inductive load; and a connecting member for supplying the deep region with a source potential, where the connecting member is configurable to connect to the drain electrode when the drain electrode is connected to the inductive load and to connect to the source electrode when the source electrode is connected to said inductive load.Type: GrantFiled: September 5, 2001Date of Patent: December 14, 2004Assignee: DENSO CorporationInventors: Yasuhiro Kitamura, Toshio Sakakibara, Kenji Kohno, Shoji Mizuno, Yoshiaki Nakayama, Hiroshi Maeda, Makio Iida, Hiroshi Fujimoto, Mitsuhiro Saitou, Hiroshi Imai, Hiroyuki Ban
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Publication number: 20020017697Abstract: A semiconductor device including a reduced surface field strength type LDMOS transistor which can prevent the breakdown of elements at channel formation portions when a reverse voltage is applied to its drain. A P well and an N well are formed in an N-type substrate to produce a double-well structure, with a source electrode being set to be equal in electric potential to the N-type substrate. The drift region of the N well has a dopant concentration to satisfy the so-called RESURF condition, which can provide a high breakdown voltage a low ON resistance. When a reverse voltage is applied to a drain electrode, a parasitic bipolar transistor comprising the N well, the P well and the N-type substrate develops to form a current-carrying path toward a substrate, so that the element breakdown at the channel formation portions is avoidable at the application of the reverse voltage.Type: ApplicationFiled: September 5, 2001Publication date: February 14, 2002Applicant: Denso CorporationInventors: Yasuhiro Kitamura, Toshio Sakakibara, Kenji Kohno, Shoji Mizuno, Yoshiaki Nakayama, Hiroshi Maeda, Makio Iida, Hiroshi Fujimoto, Mitsuhiro Saitou, Hiroshi Imai, Hiroyuki Ban
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Patent number: 6287933Abstract: A semiconductor device having a thin film resistor which comprises at least chromium, silicon and nitrogen, and formed on a substrate with having a special ratio of the chemical composition, the semiconductor device having a characteristic such that variations of the resistance value thereof due to temperature variations can be effectively suppressed.Type: GrantFiled: January 3, 1992Date of Patent: September 11, 2001Assignee: Nippondenso Co., Ltd.Inventors: Makio Iida, Shoji Miura, Kanemitsu Terada, Hiroyuki Ban, Kiyoshi Yamamoto, Katsuyoshi Oda, Yoshihiko Isobe
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Patent number: 6242792Abstract: A laser trimming is favorably performed by a strengthened laser beam energy. A level difference portion having a taper portion that is oblique with respect to the thicknesswise direction of a semiconductor substrate is formed at a surface of a semiconductor substrate. An insulating film is formed thereon and has its surface made flat, and then the thin film element is formed thereon. Thereafter, laser trimming is performed with respect to the thin film resistor. As a result, a state of interference between incident laser beam and reflected laser beam reflected from the interface between the semiconductor substrate and the insulating film is varied to thereby enable the production of a zone where laser beam energy is strengthened and a zone where laser beam energy is weakened.Type: GrantFiled: May 20, 1999Date of Patent: June 5, 2001Assignee: Denso CorporationInventors: Shoji Miura, Satoshi Shiraki, Tetsuaki Kamiya, Makio Iida
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Patent number: 6242787Abstract: A semiconductor device including a reduced surface field strength type LDMOS transistor which can prevent the breakdown of elements at channel formation portions when a reverse voltage is applied to its drain. A P well and an N well are formed in an N-type substrate to produce a double-well structure, with a source electrode being set to be equal in electric potential to the N-type substrate. The drift region of the N well has a dopant concentration to satisfy the so-called RESURF condition, which can provide a high breakdown voltage a low ON resistance. When a reverse voltage is applied to a drain electrode, a parasitic bipolar transistor comprising the N well, the P well and the N-type substrate develops to form a current-carrying path toward a substrate, so that the element breakdown at the channel formation portions is avoidable at the application of the reverse voltage.Type: GrantFiled: November 15, 1996Date of Patent: June 5, 2001Assignee: Denso CorporationInventors: Yoshiaki Nakayama, Hiroshi Maeda, Makio Iida, Hiroshi Fujimoto, Mitsuhiro Saitou, Hiroshi Imai, Hiroyuki Ban
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Patent number: 6146947Abstract: In an insulated gate type field effect transistor and a manufacturing method of the same, a diffusion region is formed in a semiconductor substrate under an oxidizing atmosphere by thermal diffusion, and a first conductivity type semiconductor layer is formed on the semiconductor substrate by vapor-phase epitaxy after the formation of the diffusion region. Thereafter, the surface of the semiconductor layer is flattened, and a gate insulating film and a gate electrode are formed on the flattened semiconductor layer. Further, a well region as well as a source region are formed in the semiconductor layer to form an insulated gate type field effect transistor. As the surface of the semiconductor layer in which the insulated gate type field effect transistor is formed is flattened, even if the embedded region is formed in the wafer, the gate-source insulation withstand voltage characteristic can be prevented from being deteriorated.Type: GrantFiled: April 3, 1998Date of Patent: November 14, 2000Assignee: Nippondenso Co., Ltd.Inventors: Naoto Okabe, Makio Iida, Norihito Tokura
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Patent number: 6104076Abstract: A semiconductor device including a reduced surface field strength type LDMOS transistor which can prevent the breakdown of elements at channel formation portions when a reverse voltage is applied to its drain. A P well and an N well are formed in an N-type substrate to produce a double-well structure, with a source electrode being set to be equal in electric potential to the N-type substrate. The drift region of the N well has a dopant concentration to satisfy the so-called RESURF condition, which can provide a high breakdown voltage a low ON resistance. When a reverse voltage is applied to a drain electrode, a parasitic bipolar transistor comprising the N well, the P well and the N-type substrate develops to form a current-carrying path toward a substrate, so that the element breakdown at the channel formation portions is avoidable at the application of the reverse voltage.Type: GrantFiled: November 15, 1996Date of Patent: August 15, 2000Assignee: Denso CorporationInventors: Yoshiaki Nakayama, Hiroshi Maeda, Makio Iida, Hiroshi Fujimoto, Mitsuhiro Saitou, Hiroshi Imai, Hiroyuki Ban
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Patent number: 6104078Abstract: A semiconductor device including a semiconductor substrate having a main surface. An insulating film is formed on the main surface of the semiconductor substrate. A semiconductor layer is placed on the insulating film. Side insulating regions extending from a surface of the semiconductor layer to the insulating film divide the semiconductor layer into element regions. The element regions are isolated from each other by the side insulating regions and the insulating film. The semiconductor substrate has a resistivity of 1.5 .OMEGA.cm or lower. A voltage at the semiconductor substrate is set to a given voltage.Type: GrantFiled: September 30, 1997Date of Patent: August 15, 2000Assignee: DENSO CorporationInventors: Makio Iida, Mitsuhiro Saitou, Akitaka Murata, Hiroyuki Ban, Tadashi Suzuki, Toshio Sakakibara, Takayuki Sugisaka, Shoji Miura
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Patent number: 5989970Abstract: Even when a contact hole is formed before thin-film resistor formation, a contact area exposed in the contact hole is prevented from damaging. A semiconductor element is formed in a silicon semiconductor substrate and an oxide film is formed on the surface of the semiconductor substrate. Then, a contact hole is formed on the oxide film and moreover, a CrSiN film serving as a thin-film resistor and a TiW film serving as a barrier metal are formed on the oxide film. The TiW film is patterned by a mask and the CrSiN film is patterned through chemical dry etching. Finally, an Al electrode is formed on the semiconductor element and the CrSiN film through the contact hole and moreover a protective film is formed thereon.Type: GrantFiled: December 30, 1996Date of Patent: November 23, 1999Assignee: Nippondenso Co., Ltd.Inventors: Makoto Ohkawa, Makio Iida, Mikimasa Suzuki
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Patent number: 5753943Abstract: In an insulated gate type field effect transistor and a manufacturing method of the same, a diffusion region is formed in a semiconductor substrate under an oxidizing atmosphere by thermal diffusion, and a first conductivity type semiconductor layer is formed on the semiconductor substrate by vapor-phase epitaxy after the formation of the diffusion region. Thereafter, the surface of the semiconductor layer is flattened, and a gate insulating film and a gate electrode are formed on the flattened semiconductor layer. Further, a well region as well as a source region are formed in the semiconductor layer to form an insulated gate type field effect transistor. As the surface of the semiconductor layer in which the insulated gate type field effect transistor is formed is flattened, even if the embedded region is formed in the wafer, the gate-source insulation withstand voltage characteristic can be prevented from being deteriorated.Type: GrantFiled: March 7, 1996Date of Patent: May 19, 1998Assignee: Nippondenso Co., Ltd.Inventors: Naoto Okabe, Makio Iida, Norihito Tokura
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Patent number: 5747846Abstract: A non-volatile memory cell having a structure having improved integration and simplified electrode wiring structure. The programmable non-volatile memory cell of the present invention adopts a mono-layer gate scheme to simplify the electrode wiring structure and to eliminate a current leakage problem of an insulating film between electrodes. A side and bottom of a semiconductor region, which is disposed directly below a capacity electrode section with a gate insulating film interposed therebetween that compose a control electrode, are isolated from another semiconductor region and semiconductor substrate by insulating films. Thus, a high programming control voltage which is not limited by a junction yield voltage between the semiconductor regions and semiconductor substrate may be applied. Due to that, an area of the capacity electrode section of a floating electrode may be considerably reduced.Type: GrantFiled: November 23, 1994Date of Patent: May 5, 1998Assignee: Nippondenso Co., Ltd.Inventors: Makio Iida, Tetsuo Fujii, Yoshihiko Isobe
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Patent number: 5644157Abstract: A semiconductor device which can compatibly achieve the improvement of the withstand voltage and the integration degree. A PN junction between a buried collector region 3 and a collector withstand voltage region 4 is subjected to reverse bias, and a depletion layer in the PN junction reaches a side dielectric isolation region 9a which dielectrically isolates the side of the collector withstand voltage region 4. A circumferential semiconductor region 14 which is in adjacency to the collector withstand voltage with the side dielectric isolation region 9a therebetween has an electric potential that is approximate to that at a base region 5 rather than that at the buried collector region 3. As a result, the depletion layer is subjected to the effect of low electric potential from both the base region 5 and the circumferential semiconductor region 14.Type: GrantFiled: May 22, 1996Date of Patent: July 1, 1997Assignee: Nippondenso Co., Ltd.Inventors: Makio Iida, Shoji Miura, Takayuki Sugisaka, Toshio Sakakibara, Osamu Ishihara
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Patent number: 5625218Abstract: A fuse fusible type semiconductor device capable of reducing energy required for fusing and a production method of the semiconductor device. In a semiconductor device equipped with a heat-fusible thin film resistor, the thin film resistor formed on a substrate 1 through an insulating film 2 is made of chromium, silicon and tungsten, and films 7 and 8 of a insulator including silicon laminated on the upper surface of the fusing surface, aluminum films 5 are disposed on both sides of the fusing surface and a barrier film 4. This semiconductor device is produced by a lamination step of sequentially forming a first insulating film 2, a thin film resistor 3, a barrier film 4 and an aluminum film 5 on a substrate 1 for reducing drastically fusing energy, an etching step of removing the barrier film 4 and the aluminum film 5 from the fusing region 31 of the thin film resistor 3, and an oxide film formation step of depositing the insulator including silicon films 7 and 8.Type: GrantFiled: June 16, 1995Date of Patent: April 29, 1997Assignees: Nippondenso Co., Ltd., Kabushiki Kaisha Toyota Chuo KenkyushoInventors: Hideya Yamadera, Takeshi Ohwaki, Yasunori Taga, Makio Iida, Makoto Ohkawa, Hirofumi Abe, Yoshihiko Isobe