Patents by Inventor Makio Mizuno
Makio Mizuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250103225Abstract: In a computer system including a plurality of storage nodes and a control node, in a case where a storage system is deployed to a new storage node, the control node templates configuration information of an existing storage node by using a template deployment service, the control node sets a plurality of initial setting nodes, and causes the plurality of initial setting nodes to perform in parallel initial setting of converting and storing data of the existing storage node by using the template in a plurality of disks to be connected to a new storage node, and the new storage node is connected to the disks in which the initial setting is performed, and imports configuration information of the existing storage so that the storage system is deployed.Type: ApplicationFiled: March 7, 2024Publication date: March 27, 2025Applicant: HITACHI, LTD.Inventors: Makio MIZUNO, Takahiro YAMAMOTO, Yoshinori OHIRA, Norio SHIMOZONO, Takeru CHIBA
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Patent number: 11836391Abstract: A distributed storage system includes one or a plurality of storage units including a plurality of physical storage devices, and a plurality of computers connected to the one or plurality of storage units via a communication network. When receiving a write request for a logical volume, the computer writes write data corresponding to the write request and redundant data for making the write data redundant in a plurality of physical storage devices of the storage unit in a distributed manner, and collectively controls writing of a journal of write data for managing a write history of the write data and a journal of redundant data for managing a write history of the redundant data.Type: GrantFiled: March 11, 2022Date of Patent: December 5, 2023Assignee: Hitachi, Ltd.Inventors: Hiroto Ebara, Akira Yamamoto, Yoshinori Ohira, Masakuni Agetsuma, Makio Mizuno, Takahiro Yamamoto
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Publication number: 20230135652Abstract: A distributed storage system includes one or a plurality of storage units including a plurality of physical storage devices, and a plurality of computers connected to the one or plurality of storage units via a communication network. When receiving a write request for a logical volume, the computer writes write data corresponding to the write request and redundant data for making the write data redundant in a plurality of physical storage devices of the storage unit in a distributed manner, and collectively controls writing of a journal of write data for managing a write history of the write data and a journal of redundant data for managing a write history of the redundant data.Type: ApplicationFiled: March 11, 2022Publication date: May 4, 2023Applicant: Hitachi, Ltd.Inventors: Hiroto EBARA, Akira YAMAMOTO, Yoshinori OHIRA, Masakuni AGETSUMA, Makio MIZUNO, Takahiro YAMAMOTO
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Patent number: 11372552Abstract: To provide stable processing performance and perform an appropriate failure processing in a storage device. A storage device includes a plurality of controllers; a plurality of storage drives; and a switch device including a plurality of controller-side ports respectively connected to the plurality of controllers and a plurality of drive-side ports respectively connected to the plurality of storage drives. The switch device performs address translations between the plurality of controller-side ports and the plurality of drive-side ports.Type: GrantFiled: December 18, 2020Date of Patent: June 28, 2022Assignee: Hitachi, Ltd.Inventors: Makio Mizuno, Kentaro Shimada, Ryosuke Matsubara, Midori Kurokawa
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Patent number: 11269703Abstract: It is detected whether write data has been correctly transmitted to a storage device under a protocol for directly connecting the storage device to a processor. An information processing system including: a processor; a memory; and a storage device, the processor first transmitting to the storage device, a command to invalidate data in a data area and which is designated by a write command, the storage device invalidating the data, the processor second transmitting to the storage device, the write command to write the data into the data area, and the storage device writing the data into the data area in accordance with the write command, validating the data in a data area into which the storage device has been successful in writing the data, and maintaining the data invalidated in a data area into which the storage device has failed in writing the data.Type: GrantFiled: September 4, 2019Date of Patent: March 8, 2022Assignee: HITACHI, LTD.Inventors: Kentaro Shimada, Makio Mizuno
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Patent number: 10983580Abstract: Computer components, such as processors and storage devices, provide a performance and consumes an electric power within a range of an upper limit performance and an upper limit power consumption of a power state set for the component among a plurality of power states corresponding to a type of the component. A processor unit determines whether a budget power as a power consumption permitted for a target computer is equal to or more than a power consumption of the target computer or not. When the determination result is false, for at least one component of the target computer, the processor unit selects a power state based on at least one of a priority of an operation using the component and a data characteristic corresponding to the component among a plurality of types of power states corresponding to a type of the component as power state of the component.Type: GrantFiled: February 24, 2017Date of Patent: April 20, 2021Assignee: HITACHI, LTD.Inventors: Makio Mizuno, Masanori Takada
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Publication number: 20210109661Abstract: To provide stable processing performance and perform an appropriate failure processing in a storage device. A storage device includes a plurality of controllers; a plurality of storage drives; and a switch device including a plurality of controller-side ports respectively connected to the plurality of controllers and a plurality of drive-side ports respectively connected to the plurality of storage drives. The switch device performs address translations between the plurality of controller-side ports and the plurality of drive-side ports.Type: ApplicationFiled: December 18, 2020Publication date: April 15, 2021Inventors: Makio MIZUNO, Kentaro SHIMADA, Ryosuke MATSUBARA, Midori KUROKAWA
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Publication number: 20210034250Abstract: To provide stable processing performance and perform an appropriate failure processing in a storage device. A storage device includes a plurality of controllers; a plurality of storage drives; and a switch device including a plurality of controller-side ports respectively connected to the plurality of controllers and a plurality of drive-side ports respectively connected to the plurality of storage drives. The switch device performs address translations between the plurality of controller-side ports and the plurality of drive-side ports.Type: ApplicationFiled: March 13, 2020Publication date: February 4, 2021Inventors: Makio MIZUNO, Kentaro SHIMADA, Ryosuke MATSUBARA, Midori KUROKAWA
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Patent number: 10901626Abstract: To provide stable processing performance and perform an appropriate failure processing in a storage device. A storage device includes a plurality of controllers; a plurality of storage drives; and a switch device including a plurality of controller-side ports respectively connected to the plurality of controllers and a plurality of drive-side ports respectively connected to the plurality of storage drives. The switch device performs address translations between the plurality of controller-side ports and the plurality of drive-side ports.Type: GrantFiled: March 13, 2020Date of Patent: January 26, 2021Assignee: HITACHI, LTD.Inventors: Makio Mizuno, Kentaro Shimada, Ryosuke Matsubara, Midori Kurokawa
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Patent number: 10732872Abstract: Provided is a storage system that includes a plurality of storage devices; a controller that controls the storage device including a processor and a memory; and a data transfer path connecting each of the storage devices to the controller. The storage device is divided into a plurality of groups. The controller specifies the storage device belonging to each of the plurality of groups among the plurality of storage devices connected via the plurality of independent data transfer paths, receives an access request to specify the storage device to be accessed, and designates the different data transfer paths for each group of the specified storage devices. The storage device performs data transfer by a connection-less protocol according to the designated data transfer path.Type: GrantFiled: February 27, 2017Date of Patent: August 4, 2020Assignee: HITACHI, LTD.Inventors: Shotaro Shintani, Kentaro Shimada, Makio Mizuno, Sadahiro Sugimoto
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Publication number: 20200159605Abstract: It is detected whether write data has been correctly transmitted to a storage device under a protocol for directly connecting the storage device to a processor. An information processing system including: a processor; a memory; and a storage device, the processor first transmitting to the storage device, a command to invalidate data in a data area and which is designated by a write command, the storage device invalidating the data, the processor second transmitting to the storage device, the write command to write the data into the data area, and the storage device writing the data into the data area in accordance with the write command, validating the data in a data area into which the storage device has been successful in writing the data, and maintaining the data invalidated in a data area into which the storage device has failed in writing the data.Type: ApplicationFiled: September 4, 2019Publication date: May 21, 2020Applicant: Hitachi, Ltd.Inventors: Kentaro Shimada, Makio Mizuno
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Publication number: 20190339905Abstract: There is provided a storage apparatus and an information processing method which can improve processing performance. In the storage apparatus, the controller generates a queue group including a plurality of command queues in which different priorities are set, in the controller itself or in the storage device, and posts the command requiring a faster processing among commands for the storage device in the command queue with a higher priority, and the storage device sequentially and repeatedly performs rounds in which the command is fetched from the command queue with a corresponding priority to be processed, for each priority and at this time, the storage device fetches and processes more commands in the round with a higher priority.Type: ApplicationFiled: March 17, 2016Publication date: November 7, 2019Inventors: Makio MIZUNO, Masanori TAKADA, Sadahiro SUGIMOTO
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Patent number: 10459791Abstract: A storage device according to an embodiment of the present invention has a plurality of storage nodes, each of which has a plurality of logical ports having send and receive queues for a communication request and an identification number, and an internal network for connecting the plurality of storage nodes with one another. The storage nodes each have, as the logical ports, a data communication logical port used for data communication with other storage nodes and an error communication logical port used to notify the other storage nodes of a state of the data communication logical port. When detecting an occurrence of transition of the data communication logical port to an error state, the storage node uses the error communication logical port to notify the other storage nodes of the identification number and the state of the data communication logical port.Type: GrantFiled: February 26, 2015Date of Patent: October 29, 2019Assignee: Hitachi, Ltd.Inventors: Katsuya Tanaka, Makio Mizuno
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Publication number: 20190258599Abstract: Provided is a storage system that includes a plurality of storage devices; a controller that controls the storage device including a processor and a memory; and a data transfer path connecting each of the storage devices to the controller. The storage device is divided into a plurality of groups. The controller specifies the storage device belonging to each of the plurality of groups among the plurality of storage devices connected via the plurality of independent data transfer paths, receives an access request to specify the storage device to be accessed, and designates the different data transfer paths for each group of the specified storage devices. The storage device performs data transfer by a connection-less protocol according to the designated data transfer path.Type: ApplicationFiled: February 27, 2017Publication date: August 22, 2019Applicant: HITACHI, LTD.Inventors: Shotaro SHINTANI, Kentaro SHIMADA, Makio MIZUNO, Sadahiro SUGIMOTO
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Publication number: 20190250693Abstract: Computer components, such as processors and storage devices, provide a performance and consumes an electric power within a range of an upper limit performance and an upper limit power consumption of a power state set for the component among a plurality of power states corresponding to a type of the component. A processor unit determines whether a budget power as a power consumption permitted for a target computer is equal to or more than a power consumption of the target computer or not. When the determination result is false, for at least one component of the target computer, the processor unit selects a power state based on at least one of a priority of an operation using the component and a data characteristic corresponding to the component among a plurality of types of power states corresponding to a type of the component as power state of the component.Type: ApplicationFiled: February 24, 2017Publication date: August 15, 2019Inventors: Makio MIZUNO, Masanori TAKADA
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Patent number: 10296429Abstract: A storage subsystem comprises one or more volumes, and multiple nodes having multiple control packages interconnected via an intra-node communication path, wherein the control packages of different nodes are interconnected via an inter-node communication path having a lower transmission path capacity than the intra-node communication path. When the host computer accesses a volume, access is enabled via any of at least two or more control packages out of the multiple control packages, and the priority for issuing access requests to the relevant volume is determined in each of the control packages. When the storage subsystem detects failure, it changes the priorities determined for the control packages according to the failure occurrence portion, and notifies the same to the host computer. The host computer determines the control package being the issue destination of the access request based on the notified priority.Type: GrantFiled: July 25, 2014Date of Patent: May 21, 2019Assignee: HITACHI, LTD.Inventors: Tomohiro Kawaguchi, Norio Simozono, Hideo Saito, Makio Mizuno
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Patent number: 10229062Abstract: A storage system includes a plurality of controllers each including a processor module and a memory, and a relay unit to relay a communication between the processor modules. The relay unit executes assignment determination to determine one of the processor module of a first controller and the processor module of a second controller is a processor module processing a command stored in the memory. The first controller includes memory storing the command, and the second controller is any of the controllers other than the first controller. When the relay unit determines the command of the processor module of the first controller, the relay unit notifies storage location information of the command to the processor module of the first controller, and when the relay unit determines the command to be processed by the processor module of the second controller, the relay unit transfer the command to the second controller.Type: GrantFiled: July 11, 2014Date of Patent: March 12, 2019Assignee: HITACHI, LTD.Inventors: Makio Mizuno, Norio Shimozono, Katsuya Tanaka
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Publication number: 20180011763Abstract: A storage device according to an embodiment of the present invention has a plurality of storage nodes, each of which has a plurality of logical ports having send and receive queues for a communication request and an identification number, and an internal network for connecting the plurality of storage nodes with one another. The storage nodes each have, as the logical ports, a data communication logical port used for data communication with other storage nodes and an error communication logical port used to notify the other storage nodes of a state of the data communication logical port. When detecting an occurrence of transition of the data communication logical port to an error state, the storage node uses the error communication logical port to notify the other storage nodes of the identification number and the state of the data communication logical port.Type: ApplicationFiled: February 26, 2015Publication date: January 11, 2018Inventors: Katsuya TANAKA, Makio MIZUNO
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Patent number: 9696922Abstract: A storage controller has a processor, a volatile first cache memory that is coupled to the processor and that temporarily stores data, a nonvolatile second cache memory that is coupled to a microprocessor and that temporarily stores data, and a battery that is configured to supply electrical power to at least the processor and the first cache memory when a power stoppage has occurred. The second cache memory includes a dirty data area for storing dirty data, which is data that is not stored in the storage device, and a remaining area other than the dirty data area. When a power stoppage has occurred, the processor stores as target data in the remaining area of the second cache memory either all or a part of the data stored in the first cache memory.Type: GrantFiled: December 24, 2013Date of Patent: July 4, 2017Assignee: Hitachi, Ltd.Inventors: Naoya Okada, Yusuke Nonaka, Akihiko Araki, Shintaro Kudo, Makio Mizuno
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Publication number: 20170177485Abstract: A storage system includes a plurality of controllers each including a processor module and a memory, and a relay unit to relay a communication between the processor modules. The relay unit executes assignment determination to determine one of the processor module of a first controller and the processor module of a second controller is a processor module processing a command stored in the memory. The first controller includes memory storing the command, and the second controller is any of the controllers other than the first controller. When the relay unit determines the command of the processor module of the first controller, the relay unit notifies storage location information of the command to the processor module of the first controller, and when the relay unit determines the command to be processed by the processor module of the second controller, the relay unit transfer the command to the second controller.Type: ApplicationFiled: July 11, 2014Publication date: June 22, 2017Applicant: HITACHI, LTD.Inventors: Makio MIZUNO, Norio SHIMOZONO, Katsuya TANAKA