Patents by Inventor Makio Okada
Makio Okada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9659888Abstract: Even when a thermal stress is applied to an electrode pad, the electrode pad is prevented from being moved. A substrate of a semiconductor chip has a rectangular planar shape. The semiconductor chip has a plurality of electrode pads. The center of a first electrode pad is positioned closer to the end of a first side in the direction along the first side of the substrate as compared to the center of a first opening. Thus, in a part of the first electrode pad covered with an insulating film, a width of the part closer to the end of the first side in the direction along the first side is larger than another width of the part opposite to the above-mentioned width.Type: GrantFiled: February 12, 2016Date of Patent: May 23, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Makio Okada, Takehiko Maeda
-
Publication number: 20160163667Abstract: Even when a thermal stress is applied to an electrode pad, the electrode pad is prevented from being moved. A substrate of a semiconductor chip has a rectangular planar shape. The semiconductor chip has a plurality of electrode pads. The center of a first electrode pad is positioned closer to the end of a first side in the direction along the first side of the substrate as compared to the center of a first opening. Thus, in a part of the first electrode pad covered with an insulating film, a width of the part closer to the end of the first side in the direction along the first side is larger than another width of the part opposite to the above-mentioned width.Type: ApplicationFiled: February 12, 2016Publication date: June 9, 2016Inventors: Makio Okada, Takehiko Maeda
-
Patent number: 9299632Abstract: Even when a thermal stress is applied to an electrode pad, the electrode pad is prevented from being moved. A substrate of a semiconductor chip has a rectangular planar shape. The semiconductor chip has a plurality of electrode pads. The center of a first electrode pad is positioned closer to the end of a first side in the direction along the first side of the substrate as compared to the center of a first opening. Thus, in a part of the first electrode pad covered with an insulating film, a width of the part closer to the end of the first side in the direction along the first side is larger than another width of the part opposite to the above-mentioned width.Type: GrantFiled: August 14, 2014Date of Patent: March 29, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Makio Okada, Takehiko Maeda
-
Publication number: 20150061159Abstract: Even when a thermal stress is applied to an electrode pad, the electrode pad is prevented from being moved. A substrate of a semiconductor chip has a rectangular planar shape. The semiconductor chip has a plurality of electrode pads. The center of a first electrode pad is positioned closer to the end of a first side in the direction along the first side of the substrate as compared to the center of a first opening. Thus, in a part of the first electrode pad covered with an insulating film, a width of the part closer to the end of the first side in the direction along the first side is larger than another width of the part opposite to the above-mentioned width.Type: ApplicationFiled: August 14, 2014Publication date: March 5, 2015Inventors: Makio Okada, Takehiko Maeda
-
Patent number: 8597989Abstract: The yield of semiconductor devices is improved. In an upper die of a resin molding die including a pair of the upper die and a lower die, by lengthening the radius of the cross section of an inner peripheral surface of a second corner part facing an injection gate of a cavity more than that of the other corner part, a void contained in a resin in resin injection can be pushed out into an air vent without allowing the void to remain in the second corner part of the cavity. Consequently, the occurrence of the void in the cavity can be prevented and then the occurrence of the appearance defect of the semiconductor device can be prevented.Type: GrantFiled: December 24, 2012Date of Patent: December 3, 2013Assignee: Renesas Electronics CorporationInventors: Makio Okada, Hidetoshi Kuraya, Toshio Tanabe, Yoshinori Fujisaki, Kotaro Arita
-
Patent number: 8349661Abstract: The yield of semiconductor devices is improved. In an upper die of a resin molding die including a pair of the upper die and a lower die, by lengthening the radius of the cross section of an inner peripheral surface of a second corner part facing an injection gate of a cavity more than that of the other corner part, a void contained in a resin in resin injection can be pushed out into an air vent without allowing the void to remain in the second corner part of the cavity. Consequently, the occurrence of the void in the cavity can be prevented and then the occurrence of the appearance defect of the semiconductor device can be prevented.Type: GrantFiled: January 12, 2012Date of Patent: January 8, 2013Assignee: Renesas Electronics CorporationInventors: Makio Okada, Hidetoshi Kuraya, Toshio Tanabe, Yoshinori Fujisaki, Kotaro Arita
-
Publication number: 20120178220Abstract: The yield of semiconductor devices is improved. In an upper die of a resin molding die including a pair of the upper die and a lower die, by lengthening the radius of the cross section of an inner peripheral surface of a second corner part facing an injection gate of a cavity more than that of the other corner part, a void contained in a resin in resin injection can be pushed out into an air vent without allowing the void to remain in the second corner part of the cavity. Consequently, the occurrence of the void in the cavity can be prevented and then the occurrence of the appearance defect of the semiconductor device can be prevented.Type: ApplicationFiled: January 12, 2012Publication date: July 12, 2012Inventors: Makio Okada, Hidetoshi Kuraya, Toshio Tanabe, Yoshinori Fujisaki, Kotaro Arita
-
Patent number: 6590286Abstract: A land grid array semiconductor device provides greater positioning accuracy for an external electrode with respect to a mounting substrate. External electrodes are arranged on one surface of a substrate in area array. The external electrode includes an external electrode pad and an external electrode interconnection. Each external electrode pad includes a first pad layer having a cylindrical shape and a second pad layer covering the surface of the first pad layer and having a conical shape.Type: GrantFiled: October 23, 2001Date of Patent: July 8, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Makio Okada, Yasushi Kasatani, Tomoaki Hashimoto
-
Publication number: 20020153608Abstract: A main object of the present invention is to provide a land grid array type semiconductor device which has been improved to provide greater positioning accuracy for an external electrode with respect to a mounting substrate. An external electrode is arranged in one surface of a substrate in area array. The external electrode includes an external electrode pad and an external electrode interconnection. The external electrode pad includes a first pad layer formed in a cylinder shape and a second pad layer formed to cover the surface of the first pad layer in a cone shape.Type: ApplicationFiled: October 23, 2001Publication date: October 24, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Makio Okada, Yasushi Kasatani, Tomoaki Hashimoto
-
Patent number: 5223738Abstract: The present invention relates to a leadframe having slits around a semiconductor device forming area to absorb distortion or warpage of the leadframe because of the difference in the coefficients of thermal expansion of the leadframe and a sealing resin. The present invention is directed to limiting shifting of the outer leads caused by distortion or contraction of the leadframe and preventing cutting of the outer leads in a tie bar cutting process. To achieve these goals, positioning holes are provided on the inner portion of the leadframe in the vicinity of the tie bars at the three corners of the semiconductor device forming area but not at a corner where the resin injecting portion is located.Type: GrantFiled: April 15, 1992Date of Patent: June 29, 1993Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Makio Okada