Patents by Inventor Makio Uchida
Makio Uchida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220344063Abstract: A nursing support system and a report generating device are disclosed. The nursing support system includes: a detection device for detecting the body of a nursing recipient to obtain detection data related to the physical status of the nursing recipient; a first report generating device for generating, according to the detection data, evaluation indexes based on international evaluation standards, i.e., international evaluation standard data, and generating a nursing report for the nursing recipient by analyzing the international evaluation standard data, the international evaluation standards being standards for evaluating human health status; and an output device for outputting the nursing report.Type: ApplicationFiled: October 31, 2019Publication date: October 27, 2022Inventors: Masaki MATSUMORI, Tatsuhiko MIYATA, XiaoLie LIN, Eiji YAMANAKA, Kunihiko MIYAZAKI, Makio UCHIDA, Ziyi FU
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Patent number: 8859883Abstract: A photovoltaic power generation system includes a plurality of power generation panels and a power conditioner. The power generation panels and a radiation source are placed in a solar cell storage room buried typically in the ground. The radiation source includes radioactive waste generated in reprocessing of spent nuclear fuel. Each power generation panel has a phosphor member and a moderator member, which are disposed in that order on solar cells placed on a board. Radiation (for example, a gamma ray) emitted from the radiation source is injected on the power generation panel and is moderated by the moderator member. When the gamma ray with the reduced energy (below 100 keV) is injected on the phosphor member, it emits visible light. When the visible light is injected on the solar cells, electric power is generated.Type: GrantFiled: February 24, 2011Date of Patent: October 14, 2014Assignee: Hitachi, Ltd.Inventors: Yasuhiro Shinkai, Makio Uchida, Ayako Kumasaka, Jun'ichi Hirota
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Publication number: 20110259399Abstract: A photovoltaic power generation system includes a plurality of power generation panels and a power conditioner. The power generation panels and a radiation source are placed in a solar cell storage room buried typically in the ground. The radiation source includes radioactive waste generated in reprocessing of spent nuclear fuel. Each power generation panel has a phosphor member and a moderator member, which are disposed in that order on solar cells placed on a board. Radiation (for example, a gamma ray) emitted from the radiation source is injected on the power generation panel and is moderated by the moderator member. When the gamma ray with the reduced energy (below 100 keV) is injected on the phosphor member, it emits visible light. When the visible light is injected on the solar cells, electric power is generated.Type: ApplicationFiled: February 24, 2011Publication date: October 27, 2011Applicant: Hitachi, Ltd.Inventors: Yasuhiro SHINKAI, Makio Uchida, Ayako Kumasaka, Jun'ichi Hirota
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Patent number: 6996661Abstract: A multiport memory has a plurality of RAMs and a port expansion unit electrically connected to access ports of the RAMs. The port expansion unit includes an input circuit which allows access control information for activating the RAMs in parallel every memory cycles to be collectively inputted thereto by a plurality of memory cycles, a timing generator which generates internal clock signals capable of serially prescribing each memory cycle plural times during one cycle of a clock signal (ck), and a logic circuit capable of sequentially supplying the access control information inputted to the input circuit to the plurality of RAMs in parallel in parts every serial memory cycles synchronized with the internal clock signals. The port expansion unit allows access to the access ports with the plurality of RAMs as a single multiport memory apparently.Type: GrantFiled: July 10, 2003Date of Patent: February 7, 2006Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Masami Hasegawa, Yoichi Satoh, Yuuji Yanagisawa, Yoshio Iioka, Yoshimi Kitagawa, Makio Uchida
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Publication number: 20040107307Abstract: A multiport memory has a plurality of RAMs and a port expansion unit electrically connected to access ports of the RAMs. The port expansion unit includes an input circuit which allows access control information for activating the RAMs in parallel every memory cycles to be collectively inputted thereto by a plurality of memory cycles, a timing generator which generates internal clock signals capable of serially prescribing each memory cycle plural times during one cycle of a clock signal (ck), and a logic circuit capable of sequentially supplying the access control information inputted to the input circuit to the plurality of RAMs in parallel in parts every serial memory cycles synchronized with the internal clock signals. The port expansion unit allows access to the access ports with the plurality of RAMs as a single multiport memory apparently.Type: ApplicationFiled: July 10, 2003Publication date: June 3, 2004Applicants: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Masami Hasegawa, Yoichi Satoh, Yuuji Yanagisawa, Yoshio Iioka, Yoshimi Kitagawa, Makio Uchida
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Patent number: 6625686Abstract: A multiport memory has a plurality of RAMs and a port expansion unit electrically connected to access ports of the RAMs. The port expansion unit includes an input circuit which allows access control information for activating the RAMs in parallel every memory cycles to be collectively inputted thereto by a plurality of memory cycles, a timing generator which generates internal clock signals capable of serially prescribing each memory cycle plural times during one cycle of a clock signal (ck), and a logic circuit capable of sequentially supplying the access control information inputted to the input circuit to the plurality of RAMs in parallel in parts every serial memory cycles synchronized with the internal clock signals. The port expansion unit allows access to the access ports with the plurality of RAMs as a single multiport memory apparently.Type: GrantFiled: August 8, 2002Date of Patent: September 23, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Systems, Co., Ltd.Inventors: Masami Hasegawa, Yoichi Satoh, Yuuji Yanagisawa, Yoshio Iioka, Yoshimi Kitagawa, Makio Uchida
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Publication number: 20020194424Abstract: A multiport memory has a plurality of RAMs and a port expansion unit electrically connected to access ports of the RAMs. The port expansion unit includes an input circuit which allows access control information for activating the RAMs in parallel every memory cycles to be collectively inputted thereto by a plurality of memory cycles, a timing generator which generates internal clock signals capable of serially prescribing each memory cycle plural times during one cycle of a clock signal (ck), and a logic circuit capable of sequentially supplying the access control information inputted to the input circuit to the plurality of RAMs in parallel in parts every serial memory cycles synchronized with the internal clock signals. The port expansion unit allows access to the access ports with the plurality of RAMs as a single multiport memory apparently.Type: ApplicationFiled: August 8, 2002Publication date: December 19, 2002Applicant: Hitachi, Ltd.Inventors: Masami Hasegawa, Yoichi Satoh, Yuuji Yanagisawa, Yoshio Iioka, Yoshimi Kitagawa, Makio Uchida
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Patent number: 6480947Abstract: A multiport memory has a plurality of RAMs and a port expansion unit electrically connected to access ports of the RAMs. The port expansion unit includes an input circuit which allows access control information for activating the RAMs in parallel every memory cycles to be collectively inputted thereto by a plurality of memory cycles, a timing generator which generates internal clock signals capable of serially prescribing each memory cycle plural times during one cycle of a clock signal (ck), and a logic circuit capable of sequentially supplying the access control information inputted to the input circuit to the plurality of RAMs in parallel in parts every serial memory cycles synchronized with the internal clock signals. The port expansion unit allows access to the access ports with the plurality of RAMs as a single multiport memory apparently.Type: GrantFiled: July 15, 1999Date of Patent: November 12, 2002Assignees: Hitachi, Ltd., Hitachi Ulsi Systems Co. Ltd.Inventors: Masami Hasegawa, Yoichi Satoh, Yuuji Yanagisawa, Yoshio Iioka, Yoshimi Kitagawa, Makio Uchida
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Patent number: 5184202Abstract: A memory array is divided into a plurality of circuit blocks which each include wirings composed of electrically conductive polycrystalline silicon layers and circuit elements that will be operated by signals supplied via the wirings. Each circuit block is served with a signal via an aluminum layer. The signal supplied to the circuit block is transmitted to the circuit elements via an internal wiring. If the aluminum layer is broken, the circuit blocks formed on the remote side beyond the broken portion fail to work properly. Therefore, breakage of the aluminum layer can be easily detected. Further, since signals are supplied to the circuit blocks via an aluminum layer, the memory array operates at increased speeds.Type: GrantFiled: July 29, 1991Date of Patent: February 2, 1993Assignee: Hitachi, Ltd.Inventor: Makio Uchida
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Patent number: 5061980Abstract: A memory array is divided into a plurality of circuit blocks which each include wirings composed of electrically conductive polycrystalline silicon layers and circuit elements that will be operated by signals supplied via the wirings. Each circuit block is served with a signal via an aluminum layer. The signal supplied to the circuit block is transmitted to the circuit elements via an internal wiring. If the aluminum layer is broken, the circuit blocks formed on the remote side beyond the broken portion fail to work properly. Therefore, breakage of the aluminum layer can be easily detected. Further, since signals are supplied to the circuit blocks via an aluminum layer, the memory array operates at increased speeds.Type: GrantFiled: August 9, 1990Date of Patent: October 29, 1991Assignee: Hitachi, Ltd.Inventor: Makio Uchida
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Patent number: 4992682Abstract: A clock drive circuit device including clock drive circuits, each of which outputs a clock signal according to a predetermined logic function corresponding to the potential of condition signals, a circuit portion for executing the logic function which is composed of FETs, and has at least one FET for adjusting the FET configuration so that the number of FETs connected in series between a clock output terminal and a power source terminal as well as a ground terminal have predetermined values, respectively.Type: GrantFiled: January 9, 1989Date of Patent: February 12, 1991Assignee: Hitachi, Ltd.Inventors: Michio Asano, Makio Uchida, Toshihiro Okabe
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Patent number: 4990992Abstract: A memory array is divided into a plurality of circuit blocks which each include wirings composed of electrically conductive polycrystalline silicon layers and circuit elements that will be operated by signals supplied via the wirings. Each circuit block is served with a signal via an aluminum layer. The signal supplied to the circuit block is transmitted to the circuit elements via an internal wiring. If the aluminum layer is broken the circuit block formed on the remote side beyond the broken portion fail to work properly. Therefore, breakage of the aluminum layer can be easily detected. Further, since signals are supplied to the circuit blocks via an aluminum layer, the memory array operates at increased speeds.Type: GrantFiled: October 5, 1988Date of Patent: February 5, 1991Assignee: Hitachi, Ltd.Inventor: Makio Uchida
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Patent number: 4894804Abstract: A semiconductor integrated circuit device having a semiconductor memory wherein part of the operation of a half precharge circuit is stopped by a reset signal, complementary data lines are set to high and low levels and a plurality of word lines are simultaneously brought into a selection state in order to effect a reset operation at a high speed.Type: GrantFiled: June 28, 1988Date of Patent: January 16, 1990Assignee: Hitachi, Ltd.Inventor: Makio Uchida
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Patent number: 4782465Abstract: A memory array is divided into a plurality of circuit blocks which each include wirings composed of electrically conductive polycrystalline silicon layers and circuit elements that will be operated by signals supplied via the wirings. Each circuit block is served with a signal via an aluminum layer. The signal supplied to the circuit block is transmitted to the circuit elements via an internal wiring. If the aluminum layer is broken, the circuit blocks formed on the remote side beyond the broken portion fail to work properly. Therefore, breakage of the aluminum layer can be easily detected. Further, since signals are supplied to the circuit blocks via an aluminum layer, the memory array operates at increased speeds.Type: GrantFiled: April 21, 1987Date of Patent: November 1, 1988Assignee: Hitachi, Ltd.Inventor: Makio Uchida
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Patent number: 4758990Abstract: A semiconductor integrated circuit device having a semiconductor memory wherein part of the operation of a half precharge circuit is stopped by a reset signal, complementary data lines are set to high and low levels and a plurality of word lines are simultaneously brought into a selection state in order to effect a reset operation at a high speed.Type: GrantFiled: May 7, 1986Date of Patent: July 19, 1988Assignee: Hitachi, Ltd.Inventor: Makio Uchida