Abstract: A detector circuit and a negative voltage generating circuit capable of performing a high-speed operation are provided. A negative voltage generating circuit includes a charge pump circuit, a first voltage divider circuit that makes a voltage division between an output of the charge pump circuit and a power supply to output a detect potential, a reference voltage generating circuit that generates a reference potential, and a comparator circuit that compares the detect potential and the reference potential. The charge pump circuit is driven by an output signal of the comparator circuit and generates the negative voltage. In the first voltage divider circuit, NMOS transistors make the voltage division between the negative voltage and the power supply to obtain the detect potential.

Abstract: A detector circuit and a negative voltage generating circuit capable of performing high-speed operation are provided. A negative voltage generating circuit includes a charge pump circuit, a first voltage divider circuit that makes a voltage division between an output of the charge pump circuit and a power supply to output a detect potential, a reference voltage generating circuit that generates a reference potential, and a comparator circuit that compares the detect potential and the reference potential. The charge pump circuit is driven by an output signal of the comparator circuit and generates the negative voltage. In the first voltage divider circuit, NMOS transistors and make the voltage division between the negative voltage and the power supply to obtain the detect potential.

Abstract: A detector circuit and a negative voltage generating circuit capable of performing high-speed operation are provided. A negative voltage generating circuit includes a charge pump circuit, a first voltage divider circuit that makes a voltage division between an output of the charge pump circuit and a power supply to output a detect potential, a reference voltage generating circuit that generates a reference potential, and a comparator circuit that compares the detect potential and the reference potential. The charge pump circuit is driven by an output signal of the comparator circuit and generates the negative voltage. In the first voltage divider circuit, NMOS transistors and make the voltage division between the negative voltage and the power supply to obtain the detect potential.

Abstract: Well bias voltages are generated in accordance with a logic power supply voltage and a memory power supply voltage. The transistor included in a control circuit in a memory core is constituted of a logic transistor manufactured through the same manufacturing steps as those for the transistors of a logic formed on the same semiconductor substrate. Well bias voltages (VBB, VPP) are applied to a back gate of this logic transistor. A memory integrated with a logic on a common semiconductor substrate is provided which allows a transistor of a control circuit therein to be manufactured through the same manufacturing process as that of the logic and allows reduction of current consumption.

Abstract: The clock-generating circuit for generating a clock signal, includes a ring oscillator having an odd number of inverters connected in a ring configuration. The ring oscillator is activated to generate a clock signal when an activating signal is at a first level and is de-activated to cease generation of the clock signal when the activating signal is at a second level. A latch circuit is connected to an output node of the ring oscillator, and holds a level of the output node of the ring oscillator in response to transition of the activating signal from the first level to the second level. When the activating signal is lowered from the H level to the L level, the level of the clock signal is latched such that generation of a glitch in the clock signal will be prevented from occurring.

Abstract: A VDC circuit that supplies an internal voltage VDD1 to an internal circuit in a normal operation forces a transistor off in a burn-in test mode through input of a test signal to suppress supply of an external power supply voltage VDDH to a node. In a burn-in test mode, an external power supply voltage lower than external power supply voltage VDDH and higher than internal voltage VDD1 is supplied from an external pad.

Abstract: A tuning control circuit includes fuse devices each shifting from a conductive state to an interrupted state in response to a program input from the outside, and signal driving circuits for driving the signal levels of tuning control signals in accordance with the states of the fuse devices. A reference voltage generating circuit generates a reference voltage corresponding to a reference value of a memory array voltage of a semiconductor memory device according to the invention in accordance with an electrical resistance value which is finely adjusted in response to the tuning control signals.

Abstract: In a detector included in a VPP generating circuit in a DRAM, an external power supply potential is applied to the gate of an N-channel MOS transistor for regulating a through current of an inverter for outputting an inversion signal of an output signal of a comparator. Since a drain-source voltage of the N-channel MOS transistor can be set to be lower than a threshold voltage Vthn of the N-channel MOS transistor, an operation margin of the detector under conditions of a low voltage and a low temperature is made wider as compared with a conventional technique.

Abstract: A DRAM is provided at a portion relating to generation of a boosted potential with a filter circuit located between a detector circuit and a ring oscillator for removing a pulse-like change in level from an output signal of the detector circuit. Accordingly, temporary stop of the charge pump circuit can be prevented even when the boosted potential exceeds in a pulse-like manner the reference potential at the vicinity of the output node of the charge pump circuit, and the boosted potential can be rapidly restored to the reference potential.

Abstract: The clock generating circuit includes: an oscillator generating a reference clock signal; an EX-OR gate connected in a ring configuration; and first and second D latch circuits. The EX-OR gate inverts a clock signal to provide the inverted clock signal to the first D latch circuit when an activating signal is at H level. In this case, the clock signal is a clock signal having a clock cycle period of twice that of the reference clock signal. The EX-OR gate provides the clock signal direct to the first D latch circuit when the activating signal is set to L level. In this case, level transition of the clock signal is ceased. Hence, generation of a glitch in the clock signal is prevented from occurring.

Abstract: A DRAM is provided at a portion relating to generation of a boosted potential with a filter circuit located between a detector circuit and a ring oscillator for removing a pulse-like change in level from an output signal of the detector circuit. Accordingly, temporary stop of the charge pump circuit can be prevented even when the boosted potential exceeds in a pulse-like manner the reference potential at the vicinity of the output node of the charge pump circuit, and the boosted potential can be rapidly restored to the reference potential.

Abstract: A VDC circuit that supplies an internal voltage VDD1 to an internal circuit in a normal operation forces a transistor off in a burn-in test mode through input of a test signal to suppress supply of an external power supply voltage VDDH to a node. In a burn-in test mode, an external power supply voltage lower than external power supply voltage VDDH and higher than internal voltage VDD1 is supplied from an external pad.

Abstract: A tuning control circuit includes fuse devices each shifting from a conductive state to an interrupted state in response to a program input from the outside, and signal driving circuits for driving the signal levels of tuning control signals in accordance with the states of the fuse devices. A reference voltage generating circuit generates a reference voltage corresponding to a reference value of a memory array voltage of a semiconductor memory device according to the invention in accordance with an electrical resistance value which is finely adjusted in response to the tuning control signals.

Abstract: A capacitor (C12) is connected between a node (L) in a double boost part and the ground, and the amplitude of a repetitive pulse from the node (L) is made less than twice that of the power-supply voltage through utilization of charge and discharge of the capacitor (C12).

Abstract: Well bias voltages are generated in accordance with a logic power supply voltage and a memory power supply voltage. The transistor included in a control circuit in a memory core is constituted of a logic transistor manufactured through the same manufacturing steps as those for the transistors of a logic formed on the same semiconductor substrate. Well bias voltages (VBB, VPP) are applied to a back gate of this logic transistor. A memory integrated with a logic on a common semiconductor substrate is provided which allows a transistor of a control circuit therein to be manufactured through the same manufacturing process as that of the logic and allows reduction of current consumption.

Abstract: In an eDRAM, there are provided a VDC that down-converts an external power supply potential to generate an internal power supply potential for a sense amplifier band, and a VDC that down-converts the external power supply potential to generate an internal power supply potential for a column decoder. The response of the VDC is improved by increasing the through current of the VDC only during the period of time corresponding to an amplify operation of the sense amplifier. Therefore, current consumption is smaller than the conventional case where the through current of the VDC is set at a high constant level.

Abstract: A capacitor (C12) is connected between a node (L) in a double boost part and the ground, and the amplitude of a repetitive pulse from the node (L) is made less than twice that of the power-supply voltage through utilization of charge and discharge of the capacitor (C12).

Abstract: In an eDRAM, there are provided a VDC that down-converts an external power supply potential to generate an internal power supply potential for a sense amplifier band, and a VDC that down-converts the external power supply potential to generate an internal power supply potential for a column decoder. The response of the VDC is improved by increasing the through current of the VDC only during the period of time corresponding to an amplify operation of the sense amplifier. Therefore, current consumption is smaller than the conventional case where the through current of the VDC is set at a high constant level.

Abstract: An equalizing circuit includes a plurality of N-channel MOS transistors for respectively setting a data line to a predetermined precharge voltage. The H-level voltage Vddb of a control signal for turning on these N-channel MOS transistors is set to a range higher than the sum of the precharge voltage and a transistor threshold voltage. A Vddb generation circuit steps up an external power-supply voltage and sets a voltage Vddb in a range lower than a step-up voltage for activating a word line.

Abstract: In a detector included in a VPP generating circuit in a DRAM, an external power supply potential is applied to the gate of an N-channel MOS transistor for regulating a through current of an inverter for outputting an inversion signal of an output signal of a comparator. Since a drain-source voltage of the N-channel MOS transistor can be set to be lower than a threshold voltage Vthn of the N-channel MOS transistor, an operation margin of the detector under conditions of a low voltage and a low temperature is made wider as compared with a conventional technique.