Abstract: The disclosure concerns a semiconductor tester for testing a MUT, comprising a pattern generator; a pattern formatter; a comparator comparing a result signal from the MUT with an expectation value; a bad block memory; an AFM pre-storing pass/fail information of each of memory cells; a data compressor compressing data of pass/fail information in the AFM; a compression failure buffer memory storing data compressed; a good block register storing an address number of a good block prepared; and an address generator, wherein when the block to be compressed is a good one, the good block register sends a address number of the good block to the compress failure buffer memory.