Patents by Inventor Makoto Hamaminato

Makoto Hamaminato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10715263
    Abstract: An information processing apparatus includes a memory, and a processor coupled to the memory and configured to obtain location information indicating locations of a wireless transmitter and a wireless receiver, simulate a first power of a first reception signal at the wireless receiver in a condition that a radio signal is transmitted from the wireless transmitter, identify a first probability distribution model in accordance with the first reception signal, identify a first parameter of the first probability distribution model in accordance with the first power and a propagation environment defined by the locations of the wireless transmitter and the wireless receiver indicated by the location information, and based on the first probability distribution model using the first parameter, simulate a second power of a second reception signal at around the wireless receiver.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: July 14, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Akihiro Wada, Teruhisa Ninomiya, Makoto Hamaminato, Hiromasa Yamauchi, Kaoru Yokoo, Kensuke Sawada
  • Patent number: 10652772
    Abstract: There is provided a radio wave interference analysis apparatus configured to analyze a state of interference due to a plurality of interference signals of a plurality of interference sources on a target signal of a wireless device as an evaluation target at a reception point, the radio wave interference analysis apparatus including a memory, and a processor coupled to the memory and the processor configured to calculate a first probability of failure of reception of the target signal at the reception point due to collision of the target signal with an interference signal of the plurality of interference signals, calculate a second probability of failure of reception of the target signal at the reception point due to the interference signal of the plurality of interference sources, and output the first probability and the second probability.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: May 12, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Tatsuya Kikuzuki, Shiho Nakahara, Akihiro Wada, Hiromasa Yamauchi, Makoto Hamaminato, Teruhisa Ninomiya
  • Publication number: 20190068302
    Abstract: An information processing apparatus includes a memory, and a processor coupled to the memory and configured to obtain location information indicating locations of a wireless transmitter and a wireless receiver, simulate a first power of a first reception signal at the wireless receiver in a condition that a radio signal is transmitted from the wireless transmitter, identify a first probability distribution model in accordance with the first reception signal, identify a first parameter of the first probability distribution model in accordance with the first power and a propagation environment defined by the locations of the wireless transmitter and the wireless receiver indicated by the location information, and based on the first probability distribution model using the first parameter, simulate a second power of a second reception signal at around the wireless receiver.
    Type: Application
    Filed: August 14, 2018
    Publication date: February 28, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Akihiro WADA, Teruhisa Ninomiya, Makoto HAMAMINATO, Hiromasa Yamauchi, Kaoru Yokoo, Kensuke SAWADA
  • Publication number: 20190007852
    Abstract: There is provided a radio wave interference analysis apparatus configured to analyze a state of interference due to a plurality of interference signals of a plurality of interference sources on a target signal of a wireless device as an evaluation target at a reception point, the radio wave interference analysis apparatus including a memory, and a processor coupled to the memory and the processor configured to calculate a first probability of failure of reception of the target signal at the reception point due to collision of the target signal with an interference signal of the plurality of interference signals, calculate a second probability of failure of reception of the target signal at the reception point due to the interference signal of the plurality of interference sources, and output the first probability and the second probability.
    Type: Application
    Filed: June 27, 2018
    Publication date: January 3, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Tatsuya Kikuzuki, Shiho Nakahara, Akihiro WADA, Hiromasa Yamauchi, Makoto HAMAMINATO, Teruhisa Ninomiya
  • Publication number: 20160337152
    Abstract: A transmitter includes a phase control circuit configured to receive a first and a second modulation signals, and a power amplifier configured to receive a third modulation signal. The phase control circuit includes a variable frequency divider, a frequency division ratio being controlled by the first modulation signal; a frequency modulation D/A converter configured to modulate the frequency by the second modulation signal; and a voltage controlled oscillator, including a varactor, configured to receive a first control voltage based on the first modulation signal and a second control voltage based on the second modulation signal. At least one of a capacitance value of the varactor of the voltage controlled oscillator, a control bit number of the frequency modulation D/A converter, and a bias current value of the frequency modulation D/A converter is changed based on a data transfer rate.
    Type: Application
    Filed: July 29, 2016
    Publication date: November 17, 2016
    Inventors: Shoichi MASUI, Makoto HAMAMINATO, Kouichi KANDA, Nauman KIYANI, Maja VIDOJKOVIC, Guido DOLMANS
  • Patent number: 8375279
    Abstract: To provide a receiving device and a receiving method which achieve iterative decoding regarding concatenated codes containing a convolutional code while suppressing increase in circuit scale, a decoder and an error correcting part iteratively perform decoding and error correction corresponding to a convolutional code on soft-decision inputs corresponding to the received signal sequence. Depending on whether a decoding result matches error corrected decoded data obtained in previous processing or not, penalties are calculated corresponding to branches transiting with the respective decoded results, and a branch metric is calculated by reflecting the calculated penalties as to decrease likelihood ratio of each of the branches to which the penalties are to be added. The obtained branch metric is input to a decoder, thereby reflecting the penalty corresponding to the decoding result.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: February 12, 2013
    Assignees: Fujitsu Limited, Fujitsu Semiconductor Limited
    Inventors: Mitsuru Tomono, Naoto Yoneda, Makoto Hamaminato
  • Patent number: 8233553
    Abstract: A digital broadcast demodulator receives a tuner signal output from a tuner and carries out demodulation processing on the tuner signal by using an internal clock signal that is synchronized with a reference signal. The digital broadcast demodulator has an internal clock-signal generator and an internal clock frequency controller. The internal clock-signal generator generates the internal clock signal, and the internal clock frequency controller controls a frequency of the internal clock signal in accordance with a reception channel.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: July 31, 2012
    Assignee: Fujitsu Limited
    Inventors: Makoto Hamaminato, Naoto Adachi
  • Patent number: 8229010
    Abstract: An OFDM signal is demodulated to generate a frequency domain signal in each of a plurality of branches. A diversity combining unit combines the demodulated signals respectively obtained in each of the branches. A clock recovery unit recovers the clock for the OFDM signal. A guard correlation unit detects the phase error of the OFDM signal. A decision unit identifies a branch having high reliability. A clock error correction unit generates a correction instruction, in accordance with the average value of the phase errors in the branch having high reliability. The clock recovery unit in each of the branches respectively corrects the error of the clock in accordance with the correction instruction.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: July 24, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Naoto Adachi, Makoto Hamaminato
  • Patent number: 8135080
    Abstract: A receiver circuit in each branch has an FFT unit that performs Fourier transform on OFDM signals. A slave branch FFT window control unit determines whether an undesired wave is a preceding wave or a delay wave, and notifies a master branch of the result. In response to the notification from the slave branch, a master branch FFT window control unit controls a position of an FFT window that indicates a time range in which Fourier transform is performed on OFDM signals.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: March 13, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Naoto Adachi, Makoto Hamaminato
  • Publication number: 20110255587
    Abstract: A reception device includes: a channel estimation circuit to receive a first signal scrambled by one of N scrambling codes and transmitted through M carriers having different frequencies, and calculate N channel estimation values corresponding to N types of first specified signals based on the first signal, where N is an integer greater than or equal to 2, where M is an integer greater than or equal to 2; a channel equalization circuit to channel-equalize a second signal, which is transmitted using the one of N scrambling codes and the M carriers, based on the N channel estimation values; and a scrambling code decoding circuit to evaluate (N*M) equalized second signals based on N types of second specified signals and decode a scrambling code of the second signal from among the N scrambling codes.
    Type: Application
    Filed: April 13, 2011
    Publication date: October 20, 2011
    Applicant: FUJITSU LIMITED
    Inventors: Shimpei YOSHIKAWA, Mitsuru TOMONO, Makoto HAMAMINATO
  • Publication number: 20110239095
    Abstract: To provide a receiving device and a receiving method which achieve iterative decoding regarding concatenated codes containing a convolutional code while suppressing increase in circuit scale, a decoder and an error correcting part iteratively perform decoding and error correction corresponding to a convolutional code on soft-decision inputs corresponding to the received signal sequence. Depending on whether a decoding result matches error corrected decoded data obtained in previous processing or not, penalties are calculated corresponding to branches transiting with the respective decoded results, and a branch metric is calculated by reflecting the calculated penalties as to decrease likelihood ratio of each of the branches to which the penalties are to be added. The obtained branch metric is input to a decoder, thereby reflecting the penalty corresponding to the decoding result.
    Type: Application
    Filed: February 24, 2011
    Publication date: September 29, 2011
    Applicants: Fujitsu Limited, Fujitsu Semiconductor Limited
    Inventors: Mitsuru Tomono, Naoto Yoneda, Makoto Hamaminato
  • Publication number: 20090097576
    Abstract: A receiver circuit in each branch has an FFT unit that performs Fourier transform on OFDM signals. A slave branch FFT window control unit determines whether an undesired wave is a preceding wave or a delay wave, and notifies a master branch of the result. In response to the notification from the slave branch, a master branch FFT window control unit controls a position of an FFT window that indicates a time range in which Fourier transform is performed on OFDM signals.
    Type: Application
    Filed: July 29, 2008
    Publication date: April 16, 2009
    Applicant: FUJITSU MICROELCTRONICS LIMITED
    Inventors: Naoto ADACHI, Makoto Hamaminato
  • Publication number: 20090097577
    Abstract: An OFDM signal is demodulated to generate a frequency domain signal in each of a plurality of branches. A diversity combining unit combines the demodulated signals respectively obtained in each of the branches. A clock recovery unit recovers the clock for the OFDM signal. A guard correlation unit detects the phase error of the OFDM signal. A decision unit identifies a branch having high reliability. A clock error correction unit generates a correction instruction, in accordance with the average value of the phase errors in the branch having high reliability. The clock recovery unit in each of the branches respectively corrects the error of the clock in accordance with the correction instruction.
    Type: Application
    Filed: July 30, 2008
    Publication date: April 16, 2009
    Applicant: Fujitsu Microelectronics Limited
    Inventors: Naoto Adachi, Makoto Hamaminato
  • Publication number: 20090097593
    Abstract: In a demodulation device with a plurality of branches, the receiving quality of each branch and signal quality after composing signals from the plurality of branches is inspected. If the signal quality is good, the operation of a branch whose receiving quality of each branch is the worst is stopped. When activating a stopped branch, the synchronous detection information of an already operated branch is applied to a branch to be newly activated and time needed for a newly activated branch to become synchronous is reduced.
    Type: Application
    Filed: July 28, 2008
    Publication date: April 16, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Makoto HAMAMINATO, Naoto Adachi
  • Publication number: 20090010370
    Abstract: A digital broadcast demodulator receives a tuner signal output from a tuner and carries out demodulation processing on the tuner signal by using an internal clock signal that is synchronized with a reference signal. The digital broadcast demodulator has an internal clock-signal generator and an internal clock frequency controller. The internal clock-signal generator generates the internal clock signal, and the internal clock frequency controller controls a frequency of the internal clock signal in accordance with a reception channel.
    Type: Application
    Filed: June 27, 2008
    Publication date: January 8, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Makoto HAMAMINATO, Naoto Adachi
  • Publication number: 20070025472
    Abstract: A demodulator is provided which includes a filter filtering a signal based on pass frequency bands changed at a time of a channel search and at a time of a normal reception, and a demodulation processing unit performing an orthogonal frequency division multiplex demodulation based on the filtered signal. Also, a demodulator is provided which includes a synchronization processing unit performing a synchronization processing based on an input signal and a demodulation processing unit performing an orthogonal frequency division multiplex demodulation based on the synchronization processed signal, wherein the synchronization processing unit calculates a correlation value of a signal being a delayed input signal and the input signal, and performs the synchronization processing when the correlation value satisfies a condition.
    Type: Application
    Filed: March 10, 2006
    Publication date: February 1, 2007
    Inventor: Makoto Hamaminato
  • Patent number: 6292408
    Abstract: A semiconductor memory device which can reduce a power consumption by reducing a charging and discharging current for a gate capacity of a transistor used for pulling up a bit line which constitutes a write recovery circuit. A pair of first and second bit lines are connected to a memory cell. A potential of one of the first and second bit lines is decreased during a write cycle in accordance with write data. A first loading element is connected between a power source line and the first bit line. The power source line supplies a positive power source voltage. A second loading element is connected between the power source line and the second bit line. A first transistor is provided for pulling up the first bit line. The first transistor has a current input terminal connected to the power source line and a current output terminal connected to the first bit line. A second transistor is provided for pulling up the second bit line.
    Type: Grant
    Filed: January 7, 2000
    Date of Patent: September 18, 2001
    Inventors: Shoichiro Kawashima, Toshihiko Mori, Makoto Hamaminato
  • Patent number: 6061276
    Abstract: A semiconductor memory device which can reduce a power consumption by reducing a charging and discharging current for a gate capacity of a transistor used for pulling up a bit line which constitutes a write recovery circuit. A pair of first and second bit lines are connected to a memory cell. A potential of one of the first and second bit lines is decreased during a write cycle in accordance with write data. A first loading element is connected between a power source line and the first bit line. The power source line supplies a positive power source voltage. A second loading element is connected between the power source line and the second bit line. A first transistor is provided for pulling up the first bit line. The first transistor has a current input terminal connected to the power source line and a current output terminal connected to the first bit line. A second transistor is provided for pulling up the second bit line.
    Type: Grant
    Filed: January 26, 1998
    Date of Patent: May 9, 2000
    Assignee: Fujitsu Limited
    Inventors: Shoichiro Kawashima, Toshihiko Mori, Makoto Hamaminato
  • Patent number: 5936881
    Abstract: A semiconductor memory device includes cells arranged in a matrix formation. Each of the cells includes a driver transistor, a read transistor which is controlled by a read word line and outputs read data read from the cell to a read bit line, a write transistor which is controlled by a write word line and supplies write data supplied from a write bit line to a cell capacitor connected to a gate of the driver transistor, and a column write select transistor which is controlled by a column write select signal line and is connected to the write transistor in series. The write data is supplied to the cell capacitor via both the column write select transistor and the write transistor.
    Type: Grant
    Filed: August 18, 1998
    Date of Patent: August 10, 1999
    Assignee: Fujitsu Limited
    Inventors: Shoichiro Kawashima, Ryuhei Sasagawa, Makoto Hamaminato