Patents by Inventor Makoto HAYAFUCHI

Makoto HAYAFUCHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12108522
    Abstract: The present technology relates to a circuit board, a semiconductor device, and an electronic device for enabling effective suppression of generation of noise in a signal. The circuit board includes a reticulated conductor including a first conductor group configured by two or more conductors having a first conductor width and arranged with a first periodic width in a first direction, a second conductor group configured by two or more conductors having a second conductor width and arranged with a second periodic width in a second direction orthogonal to the first direction, and a first moving conductor group arranged at a position to which at least a part of the second conductor group is moved by a factor of 1 of the first periodic width in the first direction and is moved by a factor of 1 of a third periodic width in the second direction, the third periodic width and the second periodic width being different. The present technology can be applied to, for example, a circuit board of a semiconductor device.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: October 1, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Takashi Miyamoto, Makoto Hayafuchi
  • Patent number: 12002831
    Abstract: Effective use is achieved of a region in a proximity of a joining plane of semiconductor substrates in a semiconductor device including a stacked semiconductor substrate in which multilayer wiring layers of a plurality of semiconductor substrates are electrically connected to each other. The stacked semiconductor substrate includes plural semiconductor substrates on each of which a multilayer wiring layer is formed. In this stacked semiconductor substrate, the multilayer wiring layers are joined together and electrically connected to each other. In the proximity of a joining plane of the plurality of semiconductor substrates, a conductor is formed. This conductor is formed such that it is electrified in a direction of the joining plane.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: June 4, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Hajime Yamagishi, Eiji Sato, Akira Yamazaki, Takayuki Sekihara, Makoto Hayafuchi, Syunsuke Ishizaki
  • Publication number: 20220415956
    Abstract: To provide a solid-state image sensor in which two or more semiconductor chips are bonded together without voids occurring in their bonding surfaces despite the conductive films bonded together at a high areal ratio. The solid-state image sensor includes at least a first semiconductor chip carrying thereon one or more than one of a first conductor and a pixel array, and a second semiconductor chip which bonds to the first semiconductor chip and carries thereon one or more than one of a second conductor and a logic circuit, with the first semiconductor chip and the second semiconductor chip bonding together in such a way that the first conductor and the second conductor overlap with each other and are electrically connected to each other, and the bonding occurring such that the first conductor and the second conductor differ from each other in the area of their bonding surfaces.
    Type: Application
    Filed: July 11, 2022
    Publication date: December 29, 2022
    Applicant: SONY GROUP CORPORATION
    Inventors: Hajime YAMAGISHI, Rena KAGAWA, Yuusaku KOBAYASHI, Yutaka NISHIMURA, Makoto HAYAFUCHI, Hayato GOUJI, Natsuhiro AOTA
  • Publication number: 20210351219
    Abstract: Effective use is achieved of a region in a proximity of a joining plane of semiconductor substrates in a semiconductor device including a stacked semiconductor substrate in which multilayer wiring layers of a plurality of semiconductor substrates are electrically connected to each other. The stacked semiconductor substrate includes plural semiconductor substrates on each of which a multilayer wiring layer is formed. In this stacked semiconductor substrate, the multilayer wiring layers are joined together and electrically connected to each other. In the proximity of a joining plane of the plurality of semiconductor substrates, a conductor is formed. This conductor is formed such that it is electrified in a direction of the joining plane.
    Type: Application
    Filed: August 2, 2019
    Publication date: November 11, 2021
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hajime YAMAGISHI, Eiji SATO, Akira YAMAZAKI, Takayuki SEKIHARA, Makoto HAYAFUCHI, Syunsuke ISHIZAKI
  • Publication number: 20210352801
    Abstract: The present technology relates to a circuit board, a semiconductor device, and an electronic device for enabling effective suppression of generation of noise in a signal. The circuit board includes a reticulated conductor including a first conductor group configured by two or more conductors having a first conductor width and arranged with a first periodic width in a first direction, a second conductor group configured by two or more conductors having a second conductor width and arranged with a second periodic width in a second direction orthogonal to the first direction, and a first moving conductor group arranged at a position to which at least a part of the second conductor group is moved by a factor of 1 of the first periodic width in the first direction and is moved by a factor of 1 of a third periodic width in the second direction, the third periodic width and the second periodic width being different. The present technology can be applied to, for example, a circuit board of a semiconductor device.
    Type: Application
    Filed: August 28, 2019
    Publication date: November 11, 2021
    Inventors: TAKASHI MIYAMOTO, MAKOTO HAYAFUCHI
  • Publication number: 20190115387
    Abstract: To provide a solid-state image sensor in which two or more semiconductor chips are bonded together without voids occurring in their bonding surfaces despite the conductive films bonded together at a high areal ratio. The solid-state image sensor includes at least a first semiconductor chip carrying thereon one or more than one of a first conductor and a pixel array, and a second semiconductor chip which bonds to the first semiconductor chip and carries thereon one or more than one of a second conductor and a logic circuit, with the first semiconductor chip and the second semiconductor chip bonding together in such a way that the first conductor and the second conductor overlap with each other and are electrically connected to each other, and the bonding occurring such that the first conductor and the second conductor differ from each other in the area of their bonding surfaces.
    Type: Application
    Filed: March 3, 2017
    Publication date: April 18, 2019
    Applicant: SONY CORPORATION
    Inventors: Hajime YAMAGISHI, Rena KAGAWA, Yuusaku KOBAYASHI, Yutaka NISHIMURA, Makoto HAYAFUCHI, Hayato GOUJI, Natsuhiro AOTA