Abstract: A thermoplastic resin reinforced sheet material that easily corresponds to a Vf value and that is prevented from being curled, and a method for manufacturing such a thermoplastic resin reinforced sheet material. The thermoplastic resin reinforced sheet material (1) includes: a reinforced fiber sheet material (2) which is formed into a sheet shape by drawing and aligning a plurality of reinforcing fibers in a predetermined direction and whose weight per unit area is 80 g/m2 or less; a fabric (3) which is formed of a thermoplastic resin fiber material having a fineness of 5.6 decitex to 84 decitex and whose basis weight per unit area is 5 g/m2 to 90 g/m2; and a thermoplastic resin material for bonding (4) which is melted or softened at a temperature lower than a melting temperature of the fabric (3) and which discretely causes the reinforced fiber sheet material (2) and the fabric (3) to adhere.

Abstract: A nonvolatile semiconductor memory device of the present invention includes: a first booster circuit for generating a first voltage higher than a voltage supplied by an external power source, the first booster circuit being used for writing or deleting of data; a second booster circuit for generating a second voltage higher than the voltage supplied by the external power source, the second booster being used for reading of data; a regulator for controlling the first voltage, the regulator being connected to an output terminal of the first booster circuit; and a reference voltage generator circuit for generating a reference voltage input to the regulator.

Abstract: A nonvolatile semiconductor memory device of the present invention includes: a first booster circuit for generating a first voltage higher than a voltage supplied by an external power source, the first booster circuit being used for writing or deleting of data; a second booster circuit for generating a second voltage higher than the voltage supplied by the external power source, the second booster being used for reading of data; a regulator for controlling the first voltage, the regulator being connected to an output terminal of the first booster circuit; and a reference voltage generator circuit for generating a reference voltage input to the regulator.

Abstract: A semiconductor storage device has a leak-monitoring capacitor connected to a bit line pre-charge potential generator, and a pre-charging transistor for charging one end of the leak-monitoring capacitor with a first potential (Vcc). The bit line pre-charge potential generator discharges from the leak-monitoring capacitor an amount of electric charges corresponding to a leak generated at a bit line pre-charge potential line which is connected with bit lines. A refresh timer circuit generates a clock signal in a cycle corresponding to a time in which the potential of the one end of the leak-monitoring capacitor decreases from the first potential (Vcc) to a second potential.

Abstract: A semiconductor memory device includes at least one memory block comprising: a plurality of word lines; a plurality of bit lines; and a plurality of memory cells each including a first switching element and a capacitor which is connected to the bit line via the first switching element, a node comprising a capacitance member having a predetermined capacitance, a second switching element for connecting the bit line to the node, a bit line precharge circuit, a capacitance member precharge circuit, and a control circuit for controlling the first switching element so as to connect electrically the memory cell which is coupled to the selected word line of a read operation to the corresponding bit line, and for controlling the second switching element so as to connect electrically the selected bit line of the read operation to the node comprising the precharged capacitance member, whereby changing the electric potential of the selected bit line so as to apply a predetermined voltage signal to the capacitor of the se

Abstract: A semiconductor memory device including a write protect information element for storing write permit information or write protect information for a word line or a bit line, and a write protect detection element for outputting a write permit or protect signal to a write circuit in accordance with the information stored in the write protect information element for the word line or bit line selected by a row decoder or a column decoder. When the write circuit receives a write protect signal output from the write protect detection means in the case that the write protect information means stores write protect information, the write circuit does not output a data signal.

Abstract: The nonvolatile semiconductor memory device of the invention includes: bit-line pairs; word lines; memory cells each including a capacitor having a ferroelectric film between electrodes thereof, and a switching element connected to one of the word lines, one of the electrodes of the capacitor being connected to one bit line of the bit-line pairs via the switching element, the other electrode of the capacitor being connected to a common cell plate; sense amplifiers each connected to one of the bit-line pairs; a row decoder for selecting one of the word lines corresponding to an input row address; and a column decoder for selecting at least one of the bit-line pairs corresponding to an input column address. The device further includes: a first driving circuit for precharging the bit lines to a first potential; and a second driving circuit for precharging again the bit-line pair selected by the column decoder to a second potential which is different from the first potential.

Abstract: A semiconductor memory includes a memory cell for storing data; a bit-line pair to be charged to an electric potential corresponding to the data stored in the memory cell; a data-line pair to be electrically connected to the bit-line pair; and a main amplifier for amplifying an electric potential difference of the data-line pair and outputting a signal corresponding to the data. The main amplifier restrains itself from outputting the signal corresponding to the data until the electric potential difference of the data-line pair becomes higher than a predetermined value.

Abstract: A system memory which includes a plurality of memory cells capable of functioning as ROMS or RAMs and being arranged in an arbitrary minimum unit. The read only area includes the memory cells functioning as the ROMS, and the write and read area includes the memory cells functioning as the RAMs. The read only areas and the write and read areas can be mixed and arranged in a memory space of the system memory without discontinuity nor a overlap. In a microcomputer including the system memory, a program is stored in the read only area, and data is stored in the write and read area.

Abstract: A semiconductor memory device is disclosed. The semiconductor memory device includes: memory cells for storing data; bit-line pairs connected to the memory cells; a bit-line precharge signal generating circuit for generating bit-line precharge signals in order to precharge the bit-line pairs to a prescribed potential; switching-element pairs for electrically connecting the bit-line pairs to data-line pairs; and column decoders each applying a column select signal to the corresponding switching-element pair in accordance with column addresses to be input. In the semiconductor memory device, a condition of V.sub.P .ltoreq.V.sub.A .ltoreq.V.sub.p +V.sub.T is substantially satisfied, where V.sub.P represents the prescribed potential to which the bit-line pairs are precharged in accordance with the bit-line precharge signals generated by the bit-line precharge signal generating circuit, V.sub.T represents a threshold voltage of each of the switching-element pairs, and V.sub.

Abstract: A ring oscillator includes a plurality of inverters, a leakage current generating part, and a current controlling part. The current controlling part supplies the inverters with a source current in accordance with a value of a leakage current generated from the leakage current generating part. The leakage current generated from the leakage current generating part is correlated with a leakage current generated from a memory cell. The oscillating frequency of the ring oscillator can be varied in accordance with the leakage current generated from the leakage current generating part.

Abstract: A semiconductor memory device including a write protect information element for storing write permit information or write protect information for a word line or a bit line, and a write protect detection element for outputting a write permit or protect signal to a write circuit in accordance with the information stored in the write protect information element for the word line or bit line selected by a row decoder or a column decoder. When the write circuit receives a write protect signal output from the write protect detection means in the case that the write protect information means stores write protect information, the write circuit does not output a data signal.

Abstract: The semiconductor memory device according to this invention includes both ROM cells and RAM cells mixed on one line of memory cells. The semiconductor memory device further has a redundant ROM bit line and a redundant RAM bit line. An address on the redundant ROM or RAM bit line is selected in accordance with whether the corresponding address on a defective line to be replaced with the redundant ROM or RAM bit line is a RAM or a ROM. Therefore, it is possible to redundantly recover a defective line including both ROMs and RAMs. Further, a semiconductor memory device including ROMs and RAMs mixedly can be produced in a high yield.

Abstract: A voltage dropping circuit for a semiconductor device is provided. The voltage dropping circuit includes a control unit for producing a reference voltage from a first specified voltage, an output unit for generating a second specified voltage which is a half of the first specified voltage in accordance with the reference voltage, a timer circuit for generating a driving pulse which becomes active intermittently, and a switch circuit for operating the control unit when the driving pulse is active and stopping the operation of the control unit when the driving pulse is not active.

Abstract: A control circuit for an internal voltage dropping circuit for a semiconductor load circuit includes a first transistor which turns on or off so as to permit or inhibit current from flowing in the internal voltage dropping circuit in accordance with an active/standby switch signal. A pulsating control signal having a specified duty ratio is generated and coupled to the control circuit while a semiconductor device in the load circuit is in a standby mode. The control circuit is intermittently activated at the specified duty ratio when the semiconductor device is on standby so that a current consumption can be reduced in accordance with the duty ratio.

Abstract: A peripheral circuit in a dynamic semiconductor memory device has a data line bias circuit and a timing generator circuit. The data line bias circuit has a switch connected between data lines and an internal voltage drop potential line having an intermediate potential between a power supply potential and a ground potential. When the switch is turned on, the data line bias circuit forms a current path connecting the internal voltage drop potential line and the data lines, and this current path is separated from ground. Therefore, electric current does not flow wastefully to ground.

Abstract: In a pseudo-static random access memory of the invention, refresh operations are conducted in a normal mode and a self-refresh mode. The memory includes a plurality of bit-line pairs each having two bit lines, a precharge voltage generating circuit for precharging the plurality of bit-line pairs to a first potential level during a precharge period in the normal mode, the circuit being electrically connected to the plurality of bit-line pairs during the precharge period in the normal mode; and bit line discharge circuit for discharging the bit-line pairs during a precharge period in the self-refresh mode, thereby decreasing the potential level of the bit-line pairs to a second potential level which is below the first potential level.

Abstract: A semiconductor memory device has a plurality of pairs of bit lines and one or more pairs of redundant bit lines to replace faulty bit lines, if any. The redundant bit lines are connected with a first pair of data lines, which is connected to a differential amplifier, by respective second switches, and the bit lines are connected with a second pair of data lines by respective first switches. A third switch is provided between the first and second data lines, and the second data lines are connected to or disconnected from the first data lines by the third switch. There are also provided column decoders connected to the respective first switches and redundant column decoders connected to both the respective second switches and the third switch. When either redundant column decoder outputs a redundant signal for connecting the redundant bit lines to the first data lines, the third switch is turned off to disconnect the second data lines from the first data lines and therefore from the differential amplifier.

Abstract: An internal address determining device for a semiconductor memory device has a refresh counter storing refresh addresses and an expanded nibble counter storing nibble addresses. External row and column addresses and a strobe signal are input to an input section. The device also has first and second multiplexers, first and second latch circuits for latching output from the first and second multiplexers, respectively, and a timing circuit for controlling operation timing of the first and second multiplexers by generating one of an external row address signal select signal, an external column address select signal, a refresh address select signal, and a nibble address select signal. In response to one of those control signals, one of the multiplexers selects and outputs a corresponding address signal.

Abstract: When a common source line of sense amplifiers in a semiconductor memory device is pulled down via a pull-down transistor, a current level signal indicative of the level of the current which flows through the pull-down transistor is generated. The current level signal is compared with a reference level signal indicative of an allowable maximum level of the current which flows through the pull-down transistor. When the current level signal exceeds the allowable maximum level, the pull-down transistor is controlled to reduce the current flowing therethrough.