Abstract: To provide a composition for a three-dimensional integrated circuit capable of forming a filling interlayer excellent in thermal conductivity also in a thickness direction, using agglomerated boron nitride particles excellent in the isotropy of thermal conductivity, disintegration resistance and kneading property with a resin. A composition for a three-dimensional integrated circuit, comprising agglomerated boron nitride particles which have a specific surface area of at least 10 m2/g, the surface of which is constituted by boron nitride primary particles having an average particle size of at least 0.05 ?m and at most 1 ?m, and which are spherical, and a resin (A) having a melt viscosity at 120° C. of at most 100 Pa·s.

Abstract: To provide a composition which satisfies a high K1c value, a high glass transition temperature and a low viscosity simultaneously, and which is capable of forming an interlayer filler layer for a layered semiconductor device of which stable bonding is maintained even regardless of changes of environment. A composition comprising an epoxy compound (A) having a viscosity at 25° C. of at most 50 Pa·s, an amine compound (B) having a melting point or softening point of at least 80° C., and an amine compound (C) having a melting point or softening point of less than 80° C., wherein the proportion of the amine compound (C) is at least 1 part by weight and less than 40 parts by weight per 100 parts by weight of the total amount of the amine compound (B) and the amine compound (C).

Abstract: To provide an interlayer filler composition which, in 3D lamination of semiconductor device chips, forms a highly thermally conductive filling interlayer simultaneously with the bonding of solder bumps or the like and lands between semiconductor device chips, a coating fluid and a process for producing a three-dimensional integrated circuit. An interlayer filler composition for a three-dimensional integrated circuit, which comprises a resin (A) having a melt viscosity at 120° C. of at most 100 Pa·s and a flux (B), the content of the flux (B) being at least 0.1 part by weight and at most 10 parts by weight per 100 parts by weight of the resin (A).

Abstract: To provide a three-dimensional integrated circuit laminate filled in with an interlayer filler composition having both high thermal conductivity and low linear expansion property. A three-dimensional integrated circuit laminate, which comprises a semiconductor substrate laminate having at least two semiconductor substrates each having a semiconductor device layer formed thereon laminated, and has a first interlayer filler layer containing a resin (A) and an organic filler (B) and having a thermal conductivity of at least 0.8 W/(m·K) between the semiconductor substrate.

Abstract: To provide a composition for a three-dimensional integrated circuit capable of forming a filling interlayer excellent in thermal conductivity also in a thickness direction, using agglomerated boron nitride particles excellent in the isotropy of thermal conductivity, disintegration resistance and kneading property with a resin. A composition for a three-dimensional integrated circuit, comprising agglomerated boron nitride particles which have a specific surface area of at least 10 m2/g, the surface of which is constituted by boron nitride primary particles having an average particle size of at least 0.05 ?m and at most 1 ?m, and which are spherical, and a resin (A) having a melt viscosity at 120° C. of at most 100 Pa·s.

Abstract: To provide a composition for a three-dimensional integrated circuit capable of forming a filling interlayer excellent in thermal conductivity also in a thickness direction, using agglomerated boron nitride particles excellent in the isotropy of thermal conductivity, disintegration resistance and kneading property with a resin. A composition for a three-dimensional integrated circuit, comprising agglomerated boron nitride particles which have a specific surface area of at least 10 m2/g, the surface of which is constituted by boron nitride primary particles having an average particle size of at least 0.05 ?m and at most 1 ?m, and which are spherical, and a resin (A) having a melt viscosity at 120° C. of at most 100 Pa·s.

Abstract: To provide a composition for a three-dimensional integrated circuit capable of forming a filling interlayer excellent in thermal conductivity also in a thickness direction, using agglomerated boron nitride particles excellent in the isotropy of thermal conductivity, disintegration resistance and kneading property with a resin. A composition for a three-dimensional integrated circuit, comprising agglomerated boron nitride particles which have a specific surface area of at least 10 m2/g, the surface of which is constituted by boron nitride primary particles having an average particle size of at least 0.05 ?m and at most 1 ?m, and which are spherical, and a resin (A) having a melt viscosity at 120° C. of at most 100 Pa·s.

Abstract: To provide an interlayer filler composition capable of forming a cured adhesive layer sufficiently cured and excellent in adhesion without letting voids be formed in the cured adhesive layer while minimizing leak out of a filler. An interlayer filler composition for a semiconductor device, comprises an epoxy resin (A), a curing agent (B), a filler (C) and a flux (D), has a minimum value of its viscosity at from 100 to 150° C. and satisfies the following formulae (1) and (2) simultaneously: 10<?50/?120<500 ??(1) 1,000<?150/?120 ??(2) (wherein ?50, ?120 and ?150 represent the viscosities at 50° C., 120° C. and 150° C., respectively, of the interlayer filler composition).

Abstract: To provide a three-dimensional integrated circuit laminate filled in with an interlayer filler composition having both high thermal conductivity and low linear expansion property. A three-dimensional integrated circuit laminate, which comprises a semiconductor substrate laminate having at least two semiconductor substrates each having a semiconductor device layer formed thereon laminated, and has a first interlayer filler layer containing a resin (A) and an organic filler (B) and having a thermal conductivity of at least 0.8 W/(m·K) between the semiconductor substrate.

Abstract: To provide a three-dimensional integrated circuit laminate filled in with an interlayer filler composition having both high thermal conductivity and low linear expansion property, a three-dimensional integrated circuit laminate, which comprises a semiconductor substrate laminate having at least two semiconductor substrates each having a semiconductor device layer formed thereon laminated, and has a first interlayer filler layer containing a resin (A) and an organic filler (B) and having a thermal conductivity of at least 0.8 W/(rrrK) between the semiconductor substrate.

Abstract: To provide a composition which satisfies a high K1c value, a high glass transition temperature and a low viscosity simultaneously, and which is capable of forming an interlayer filler layer for a layered semiconductor device of which stable bonding is maintained even regardless of changes of environment. A composition comprising an epoxy compound (A) having a viscosity at 25° C. of at most 50 Pa·s, an amine compound (B) having a melting point or softening point of at least 80° C., and an amine compound (C) having a melting point or softening point of less than 80° C., wherein the proportion of the amine compound (C) is at least 1 part by weight and less than 40 parts by weight per 100 parts by weight of the total amount of the amine compound (B) and the amine compound (C).

Abstract: To provide a composition for a three-dimensional integrated circuit capable of forming a filling interlayer excellent in thermal conductivity also in a thickness direction, using agglomerated boron nitride particles excellent in the isotropy of thermal conductivity, disintegration resistance and kneading property with a resin. A composition for a three-dimensional integrated circuit, comprising agglomerated boron nitride particles which have a specific surface area of at least 10 m2/g, the surface of which is constituted by boron nitride primary particles having an average particle size of at least 0.05 ?m and at most 1 ?m, and which are spherical, and a resin (A) having a melt viscosity at 120° C. of at most 100 Pa·s.

Abstract: To provide a three-dimensional integrated circuit laminate filled in with an interlayer filler composition having both high thermal conductivity and low linear expansion property. A three-dimensional integrated circuit laminate, which comprises a semiconductor substrate laminate having at least two semiconductor substrates each having a semiconductor device layer formed thereon laminated, and has a first interlayer filler layer containing a resin (A) and an organic filler (B) and having a thermal conductivity of at least 0.8 W/(m·K) between the semiconductor substrate.

Abstract: To provide an interlayer filler composition which, in 3D lamination of semiconductor device chips, forms a highly thermally conductive filling interlayer simultaneously with the bonding of solder bumps or the like and lands between semiconductor device chips, a coating fluid and a process for producing a three-dimensional integrated circuit. An interlayer filler composition for a three-dimensional integrated circuit, which comprises a resin (A) having a melt viscosity at 120° C. of at most 100 Pa·s and a flux (B), the content of the flux (B) being at least 0.1 part by weight and at most 10 parts by weight per 100 parts by weight of the resin (A).

Abstract: To provide a cleaning solution for a substrate for a semiconductor device which is excellent in the ability to remove particles, organic contaminants, metal contaminants and composite contaminants of an organic matter and a metal attached on a substrate surface, whereby the substrate surface can be highly cleaned, without being corroded. Particularly, to provide a cleaning solution which is excellent in the ability to clean low dielectric constant (Low-k) materials on which liquid is easily repelled due to hydrophobic and of which the ability to remove particles is poor. A cleaning solution for a substrate for a semiconductor device, which comprises the following components (A) and (B): (A) an organic acid (B) a nonionic surfactant having an HLB value of from 5 to less than 13.

Abstract: To provide a cleaning solution for a substrate for a semiconductor device which is excellent in the ability to remove particles, organic contaminants, metal contaminants and composite contaminants of an organic matter and a metal attached on a substrate surface, whereby the substrate surface can be highly cleaned, without being corroded. Particularly, to provide a cleaning solution which is excellent in the ability to clean low dielectric constant (Low-k) materials on which liquid is easily repelled due to hydrophobic and of which the ability to remove particles is poor. A cleaning solution for a substrate for a semiconductor device, which comprises the following components (A) and (B): (A) an organic acid (B) a nonionic surfactant having an HLB value of from 5 to less than 13.

Abstract: A cleaning solution for cleaning a substrate for semiconductor devices and a cleaning method using the said cleaning solution, which comprises at least the following components (A), (B) and (C): (A) an ethyleneoxide-type surfactant containing a hydrocarbon group which may have a substituent group except for phenyl, and a polyoxyethylene group in which a ratio (m/n) of a number (m) of carbon atoms contained in the hydrocarbon group to a number (n) of oxyethylene groups contained in the polyoxyethylene group is in the range of 1 to 1.5, the number (m) of carbon atoms is not less than 9, and the number (n) of oxyethylene groups is not less than 7; (B) water; and (C) alkali or an organic acid.

Abstract: To provide a cleaning solution for a substrate for a semiconductor device capable of removing particle contamination, organic contamination and metal contamination at the same time without corroding the substrate surface, and further having good water rinsability and capable of making the substrate surface highly clean in a short time, and a cleaning method.

Abstract: A cleaning solution for cleaning a substrate for semiconductor devices and a cleaning method using the said cleaning solution, which comprises at least the following components (A), (B) and (C): (A) an ethyleneoxide-type surfactant containing a hydrocarbon group which may have a substituent group except for phenyl, and a polyoxyethylene group in which a ratio (m/n) of a number (m) of carbon atoms contained in the hydrocarbon group to a number (n) of oxyethylene groups contained in the polyoxyethylene group is in the range of 1 to 1.5, the number (m) of carbon atoms is not less than 9, and the number (n) of oxyethylene groups is not less than 7; (B) water; and (C) alkali or an organic acid. The cleaning solution highly clean the surface of the substrate without occurrence of corrosion by removing fine particles and organic contaminants which are adhered onto the surface of the substrate.

Abstract: To provide a cleaning solution for a substrate for a semiconductor device capable of removing particle contamination, organic contamination and metal contamination at the same time without corroding the substrate surface, and further having good water rinsability and capable of making the substrate surface highly clean in a short time, and a cleaning method. A cleaning solution for a substrate for a semiconductor device, which comprises an organic acid as component (a), an organic alkaline component as component (b), a surfactant as component (c) and water as component (d) and which has a pH of at least 1.5 and less than 6.5. A method for cleaning a substrate for a semiconductor device, which comprises cleaning a substrate for a semiconductor device having a Cu film and a low dielectric constant insulating film on its surface and having CMP treatment applied thereto, by means of the above cleaning solution for a substrate for a semiconductor device.