Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a plurality of source layers, where the electrically conductive layers include word lines and source-side select gate electrodes which are located between the plurality of source layers and the word lines in a vertical direction, groups of memory openings vertically extending through the alternating stack, and groups of memory opening fill structures located in the groups of memory openings. The plurality of source layers are laterally spaced apart and electrically isolated from each other, and each respective one of the plurality of source layers contacts at least one respective group of the groups of memory opening fill structures.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory pillar structures extending through the alternating stack. Each of the memory pillar structures includes a respective memory film and a respective vertical semiconductor channel. Dielectric cores contact an inner sidewall of a respective one of the vertical semiconductor channels. A drain-select-level isolation structure laterally extends along a first horizontal direction and contacts straight sidewalls of the dielectric cores at a respective two-dimensional flat interface. The memory pillar structures may be formed on-pitch as a two-dimensional periodic array, and themay drain-select-level isolation structure may cut through upper portions of the memory pillar structures to minimize areas occupied by the drain-select-level isolation structure.

Abstract: A source-level sacrificial layer and an alternating stack of insulating layers and sacrificial material layers are formed over a substrate. Memory openings are formed through the alternating stack, and a source cavity is formed by removing the source-level sacrificial layer. A memory film is formally formed by a conformal deposition process, and a source contact layer is formed in the source cavity. Vertical semiconductor channels and drain regions are formed in remaining volumes of the memory openings on sidewalls of the source contact layer. A backside contact via structure is formed through the alternating stack and directly on a sidewall of the source contact layer.

Abstract: A lower source layer, a sacrificial source-level material layer, and an upper source layer are formed over a substrate. The lower source layer includes a recess trench in which a recessed surface of the lower source layer is vertically recessed relative to a topmost surface of the lower source layer. An alternating stack of insulating layers and spacer material layers is subsequently formed. Memory stack structures are formed through the alternating stack. A backside trench is formed through the alternating stack such that a bottom surface of the backside trench is formed within an area of the recess trench in a thickened portion of the sacrificial source-level material layer. The sacrificial source-level material layer is replaced with a source contact layer.

Abstract: A source-level sacrificial layer and an alternating stack of insulating layers and sacrificial material layers are formed over a substrate. Memory openings are formed through the alternating stack, and a source cavity is formed by removing the source-level sacrificial layer. A memory film is formally formed by a conformal deposition process, and a source contact layer is formed in the source cavity. Vertical semiconductor channels and drain regions are formed in remaining volumes of the memory openings on sidewalls of the source contact layer. A backside contact via structure is formed through the alternating stack and directly on a sidewall of the source contact layer.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory pillar structures extending through the alternating stack. Each of the memory pillar structures includes a respective memory film and a respective vertical semiconductor channel Dielectric cores contact an inner sidewall of a respective one of the vertical semiconductor channels. A drain-select-level isolation structure laterally extends along a first horizontal direction and contacts straight sidewalls of the dielectric cores at a respective two-dimensional flat interface. The memory pillar structures may be formed on-pitch as a two-dimensional periodic array, and themay drain-select-level isolation structure may cut through upper portions of the memory pillar structures to minimize areas occupied by the drain-select-level isolation structure.

Abstract: Provided is a diode element, a detecting device, and the like which solve problems of a conventional lateral diode element. In the conventional element, a semiconductor interface appears in current path between two electrodes on a surface thereof, and thus noise caused by the interface is large. The diode element includes: a first-conductive-type low carrier concentration layer; a first-conductive-type high carrier concentration layer; and a Schottky electrode and an ohmic electrode which are formed on a semiconductor surface. The low carrier layer has a carrier concentration that is lower than that of the high carrier layer. The diode element includes a first-conductive-type impurity introducing region formed below the ohmic electrode, and includes a second-conductive-type impurity introducing region so as not to be in electrical contact with the Schottky electrode on the semiconductor surface between the Schottky and the ohmic.

Abstract: Provided is a diode element, a detecting device, and the like which solve problems of a conventional lateral diode element. In the conventional element, a semiconductor interface appears in current path between two electrodes on a surface thereof, and thus noise caused by the interface is large. The diode element includes: a first-conductive-type low carrier concentration layer; a first-conductive-type high carrier concentration layer; and a Schottky electrode and an ohmic electrode which are formed on a semiconductor surface. The low carrier layer has a carrier concentration that is lower than that of the high carrier layer. The diode element includes a first-conductive-type impurity introducing region formed below the ohmic electrode, and includes a second-conductive-type impurity introducing region so as not to be in electrical contact with the Schottky electrode on the semiconductor surface between the Schottky and the ohmic.

Abstract: The present invention relates to a method of manufacturing a semiconductor device by which the length of nanowires perpendicularly formed can be fabricated with high reproducibility. The method of manufacturing a semiconductor device includes the steps of forming a first layer; forming a stop layer on the first layer, the stop layer having a higher Young's modulus than the first layer; forming a recess by partially removing the first layer and the stop layer; growing nanowires in the recess; forming a planarizing layer; removing the planarizing layer to the level of the stop layer to expose the nanowires from the surface of the planarizing layer; and forming an electrode so as to be in contact with the upper ends of the nanowires.

Abstract: A method for producing a semiconductor includes a step of preparing a substrate having a fixing portion, a step of disposing a catalyst on the fixing portion, and a step of growing a semiconductor between the catalyst and the fixing portion, wherein a eutectic temperature between the catalyst and the semiconductor is lower than that between the fixing portion and the substrate.

Abstract: The present invention relates to a method of manufacturing a semiconductor device by which the length of nanowires perpendicularly formed can be fabricated with high reproducibility. The method of manufacturing a semiconductor device includes the steps of forming a first layer; forming a stop layer on the first layer, the stop layer having a higher Young's modulus than the first layer; forming a recess by partially removing the first layer and the stop layer; growing nanowires in the recess; forming a planarizing layer; removing the planarizing layer to the level of the stop layer to expose the nanowires from the surface of the planarizing layer; and forming an electrode so as to be in contact with the upper ends of the nanowires.

Abstract: A field-effect transistor includes a semiconductor layer, at least two active regions disposed in the semiconductor layer, a source electrode in contact with one of the two active regions, a drain electrode in contact with the other active region; an insulating layer which is located between the source electrode and the drain electrode and which is disposed on the semiconductor layer, a gate electrode overlying the insulating layer, an adsorption site which is disposed between the gate electrode and the insulating layer and is used to adsorb a molecule, and a driving unit used to drive the gate electrode.

Abstract: To provide a semiconductor device including vertically formed nanowires in which parasitic capacitance is prevented from increasing and time constant associated with an operation speed is improved. Two different layers, which are a film thickness adjustment layer and a protective insulating layer, are provided as an interlayer insulating film between an electrode and a planar main surface of an electrically conductive substrate. This structural characteristic can reduce parasitic capacitance generated among the nanowires which electrically connect the planar main surface and the electrode to each other, the electrically conductive substrate, and the electrode, while controlling peel-off of a low dielectric film having a poor adhesion by separating the low dielectric film from the electrode with the protective insulating layer interposed therebetween.

Abstract: A light-emitting element array can be manufactured without the separation of a metal reflection layer. The light-emitting element array includes a plurality of light-emitting element portions provided on a substrate, at least one space of the spaces between adjacent light-emitting element portions being electrically separated from each other, wherein the metal reflection layer is provided on the substrate and under the plurality of light-emitting element portions, and a resistive layer for electrical separation between the light-emitting element portions is provided between the plurality of light-emitting element portions and the metal reflection layer. The plurality of light-emitting element portions are divided into a plurality of blocks. Each of the blocks includes a plurality of light-emitting portions. The electrical separation between the light-emitting portions can be made as electrical separation between adjacent light-emitting element portions in adjacent and different blocks.

Abstract: A light-emitting element array can be manufactured without the separation of a metal reflection layer. The light-emitting element array includes a plurality of light-emitting element portions provided on a substrate, at least one space of the spaces between adjacent light-emitting element portions being electrically separated from each other, wherein the metal reflection layer is provided on the substrate and under the plurality of light-emitting element portions, and a resistive layer for electrical separation between the light-emitting element portions is provided between the plurality of light-emitting element portions and the metal reflection layer. The plurality of light-emitting element portions are divided into a plurality of blocks. Each of the blocks includes a plurality of light-emitting portions. The electrical separation between the light-emitting portions can be made as electrical separation between adjacent light-emitting element portions in adjacent and different blocks.

Abstract: A light-emitting element array can be manufactured without the separation of a metal reflection layer. The light-emitting element array includes a plurality of light-emitting element portions provided on a substrate, at least one space of the spaces between adjacent light-emitting element portions being electrically separated from each other, wherein the metal reflection layer is provided on the substrate and under the plurality of light-emitting element portions, and a resistive layer for electrical separation between the light-emitting element portions is provided between the plurality of light-emitting element portions and the metal reflection layer. The plurality of light-emitting element portions are divided into a plurality of blocks. Each of the blocks includes a plurality of light-emitting portions. The electrical separation between the light-emitting portions can be made as electrical separation between adjacent light-emitting element portions in adjacent and different blocks.

Abstract: This invention provides a semiconductor film manufacturing method using a new separation technique and applications thereof. The semiconductor film manufacturing method of this invention includes a separation layer forming a step of hetero-epitaxially growing a separation layer (2) on a seed substrate (1), a semiconductor film forming step of forming a semiconductor film (3) on the separation layer (2), and a separation step of separating, by using the separation layer (2), the semiconductor film (3) from a composite member (Ia) formed in the semiconductor film forming step.

Abstract: A light-emitting element array can be manufactured without the separation of a metal reflection layer. The light-emitting element array includes a plurality of light-emitting element portions provided on a substrate, at least one space of the spaces between adjacent light-emitting element portions being electrically separated from each other, wherein the metal reflection layer is provided on the substrate and under the plurality of light-emitting element portions, and a resistive layer for electrical separation between the light-emitting element portions is provided between the plurality of light-emitting element portions and the metal reflection layer. The plurality of light-emitting element portions are divided into a plurality of blocks. Each of the blocks includes a plurality of light-emitting portions. The electrical separation between the light-emitting portions can be made as electrical separation between adjacent light-emitting element portions in adjacent and different blocks.

Abstract: Provided is a light control device including: a thin film transistor; and a light control element including an electrode electrically connected to the thin film transistor, in which a semiconductor region of the thin film transistor and an pixel electrode are composed of the same semiconductor layer, and the same semiconductor layer is an amorphous oxide layer including at least one of In, Ga, and Zn.

Abstract: This invention provides a semiconductor film manufacturing method using a new separation technique and applications thereof. The semiconductor film manufacturing method of this invention includes a separation layer forming a step of hetero-epitaxially growing a separation layer (2) on a seed substrate (1), a semiconductor film forming step of forming a semiconductor film (3) on the separation layer (2), and a separation step of separating, by using the separation layer (2), the semiconductor film (3) from a composite member (Ia) formed in the semiconductor film forming step.