Patents by Inventor Makoto Matsunoshita

Makoto Matsunoshita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7851884
    Abstract: A FET exhibiting excellent uniformity and productivity and having a low noise figure and high associated gain as high-frequency performance, a semiconductor chip having this FET and a semiconductor device having the semiconductor chip. The FET includes a GaAs substrate on which are built up an i-type GaAs layer, an i-type InGaAs two-dimensional electron gas layer and an n-type AlGaAs electron supply layer. A gate electrode is provided on and in linear Schottky contact with the n-type AlGaAs electron supply layer. A n-type InGaP etching stop layer and then an n-type GaAs contact layer at the same lateral position are built up on the n-type AlGaAs electron supply layer, these being spaced away from both sides of the gate electrode. A source electrode and a drain electrode are provided on the n-type GaAs contact layer and are spaced away from edges of the contact layer as electrodes that make band-shaped ohmic contact.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: December 14, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Shuji Asai, Akira Fujihara, Makoto Matsunoshita, Naoki Sakura, Seiji Ichikawa
  • Publication number: 20090288852
    Abstract: An electronic device of the present invention has a substrate; an electro-conductive pattern (electrodes) provided over the substrate; a semiconductor chip mounted over the substrate, and electrically connected with the electrodes; a resin cap provided over the substrate and composed of two or more resin layers to hollow-sealing the semiconductor chip; and an adhesive layer (metal-resin adhesion maintenance layer) bonding the resin cap with the electrode.
    Type: Application
    Filed: April 27, 2009
    Publication date: November 26, 2009
    Applicant: NEC Electronics Corporation
    Inventors: Tomoaki Hirokawa, Makoto Matsunoshita, Yuji Kakuta, Naoki Sakura
  • Publication number: 20090078966
    Abstract: A FET exhibiting excellent uniformity and productivity and having a low noise figure and high associated gain as high-frequency performance, a semiconductor chip having this FET and a semiconductor device having the semiconductor chip. The FET includes a GaAs substrate on which are built up an i-type GaAs layer, an i-type InGaAs two-dimensional electron gas layer and an n-type AlGaAs electron supply layer. A gate electrode is provided on and in linear Schottky contact with the n-type AlGaAs electron supply layer. A n-type InGaP etching stop layer and then an n-type GaAs contact layer at the same lateral position are built up on the n-type AlGaAs electron supply layer, these being spaced away from both sides of the gate electrode. A source electrode and a drain electrode are provided on the n-type GaAs contact layer and are spaced away from edges of the contact layer as electrodes that make band-shaped ohmic contact.
    Type: Application
    Filed: September 24, 2008
    Publication date: March 26, 2009
    Applicant: NEC Electronics Corporation
    Inventors: Shuji Asai, Akira Fujihara, Makoto Matsunoshita, Naoki Sakura, Seiji Ichikawa