Abstract: Pixel portions each of which has a charge storage portion formed in a semiconductor substrate 11 and a transfer gate for transferring charges stored in the charge storage portion are isolated from each other by a device isolation region in the semiconductor substrate. A buried gate electrically connected to the transfer gate is embedded in the device isolation region. The buried gate includes a gate dielectric film and gate electrode formed in a trench of the semiconductor substrate.

Abstract: A semiconductor device has a well region having a first conductivity type and formed in an upper portion of a semiconductor substrate, a gate insulating film and a gate electrode formed successively on the well region of the semiconductor substrate, a threshold voltage control layer for controlling a threshold voltage formed in the portion of the well region which is located below the gate electrode and in which an impurity of the first conductivity type has a concentration peak at a position shallower than in the well region, an extension region having a second conductivity type and formed in the well region to be located between each of the respective portions of the well region which are located below the both end portions in the gate-length direction of the gate electrode and the threshold voltage control layer, and source and drain regions each having the second conductivity type and formed outside the extension layer in connected relation thereto.

Abstract: Pixel portions each of which has a charge storage portion formed in a semiconductor substrate 11 and a transfer gate for transferring charges stored in the charge storage portion are isolated from each other by a device isolation region in the semiconductor substrate. A buried gate electrically connected to the transfer gate is embedded in the device isolation region. The buried gate includes a gate dielectric film and gate electrode formed in a trench of the semiconductor substrate.

Abstract: A semiconductor device has a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type which is formed to extend from the surface of the semiconductor substrate toward the inside thereof, a pair of second well regions of a second conductivity which are formed to extend from the surface of the semiconductor substrate toward the inside thereof in such as manner as to sandwich the first well region therebetween, and a third well region of the second conductivity type which is formed under each of the first well region and the pair of second well regions in the semiconductor substrate. The third well region electrically connects the pair of second well regions to each other. The first well region has at least a portion thereof connected to the region of the semiconductor substrate in which the third well region is not formed.

Abstract: A semiconductor device has a well region having a first conductivity type and formed in an upper portion of a semiconductor substrate, a gate insulating film and a gate electrode formed successively on the well region of the semiconductor substrate, a threshold voltage control layer for controlling a threshold voltage formed in the portion of the well region which is located below the gate electrode and in which an impurity of the first conductivity type has a concentration peak at a position shallower than in the well region, an extension region having a second conductivity type and formed in the well region to be located between each of the respective portions of the well region which are located below the both end portions in the gate-length direction of the gate electrode and the threshold voltage control layer, and source and drain regions each having the second conductivity type and formed outside the extension layer in connected relation thereto.

Abstract: A semiconductor device has a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type which is formed to extend from the surface of the semiconductor substrate toward the inside thereof, a pair of second well regions of a second conductivity which are formed to extend from the surface of the semiconductor substrate toward the inside thereof in such as manner as to sandwich the first well region therebetween, and a third well region of the second conductivity type which is formed under each of the first well region and the pair of second well regions in the semiconductor substrate. The third well region electrically connects the pair of second well regions to each other. The first well region has at least a portion thereof connected to the region of the semiconductor substrate in which the third well region is not formed.