Patents by Inventor Makoto Muneyasu
Makoto Muneyasu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160241218Abstract: In a semiconductor device, a charge pump operates in accordance with a clock signal and thereby generates a boosted voltage of a polarity which is the same as or reverse to the polarity of an input voltage. An oscillation circuit generates and outputs a clock signal. The oscillation circuit cyclically fluctuates a frequency of the clock signal within a predetermined fluctuation range. Thereby, EMI noise generated corresponding to the frequency of the clock signal for driving the charge pump is reduced.Type: ApplicationFiled: January 28, 2016Publication date: August 18, 2016Applicant: Renesas Electronics CorporationInventors: Makoto MUNEYASU, Takashi KONO
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Patent number: 8242808Abstract: A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal.Type: GrantFiled: May 12, 2011Date of Patent: August 14, 2012Assignee: Renesas Electronics CorporationInventors: Mitsuhiro Tomoeda, Makoto Muneyasu, Masahiro Hosoda
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Publication number: 20110216620Abstract: A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal.Type: ApplicationFiled: May 12, 2011Publication date: September 8, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Mitsuhiro TOMOEDA, Makoto MUNEYASU, Masahiro HOSODA
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Patent number: 7969200Abstract: A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal.Type: GrantFiled: July 28, 2010Date of Patent: June 28, 2011Assignee: Renesas Electronics CorporationInventors: Mitsuhiro Tomoeda, Makoto Muneyasu, Masahiro Hosoda
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Publication number: 20100301902Abstract: A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal.Type: ApplicationFiled: July 28, 2010Publication date: December 2, 2010Applicant: RENESAS TECHNOLOGY CORP.Inventors: Mitsuhiro TOMOEDA, Makoto Muneyasu, Masahiro Hosoda
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Patent number: 7795922Abstract: A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal.Type: GrantFiled: January 29, 2009Date of Patent: September 14, 2010Assignee: Renesas Electronics CorporationInventors: Mitsuhiro Tomoeda, Makoto Muneyasu, Masahiro Hosoda
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Publication number: 20090237114Abstract: A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal.Type: ApplicationFiled: January 29, 2009Publication date: September 24, 2009Inventors: Mitsuhiro TOMOEDA, Makoto MUNEYASU, Masahiro HOSODA
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Publication number: 20070036001Abstract: After data writing is performed by injecting electrons into a floating gate from a semiconductor substrate of a memory cell, the gate voltage is set at ?3 V, and the source voltage, the drain voltage and the substrate voltage are set at 0 V, thereby detrapping the electrons trapped in an oxide film during data writing. The gate voltage (?3 V) is set at a negative voltage value that is smaller in absolute value than the gate voltage (?10.5 V) applied during data erasing.Type: ApplicationFiled: July 27, 2006Publication date: February 15, 2007Inventors: Akihiko Kanda, Taku Ogura, Makoto Muneyasu
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Patent number: 6584020Abstract: In a bit line reference potential (VBL) generating circuit, a pad is connected via a transfer gate to a reference node in a reference stage. During a device evaluation test, the transfer gate is turned on in response to a test signal so that a voltage is applied to the reference node with a tester driver via the pad to control a potential of an output node in an output stage. Thus, the semiconductor memory device is capable of stably controlling the bit line reference potential VBL regardless of the drivability of the tester driver during the device evaluation test.Type: GrantFiled: July 23, 2001Date of Patent: June 24, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tadaaki Yamauchi, Makoto Muneyasu
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Publication number: 20020101773Abstract: In a bit line reference potential (VBL) generating circuit, a pad is connected via a transfer gate to a reference node in a reference stage. During a device evaluation test, the transfer gate is turned on in response to a test signal so that a voltage is applied to the reference node with a tester driver via the pad to control a potential of an output node in an output stage. Thus, the semiconductor memory device is capable of stably controlling the bit line reference potential VBL regardless of the drivability of the tester driver during the device evaluation test.Type: ApplicationFiled: July 23, 2001Publication date: August 1, 2002Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Tadaaki Yamauchi, Makoto Muneyasu