Abstract: An information processing apparatus (10) includes a controller (11) that acquires an image containing a figure and a character string and generates association information indicating an association between the figure and the character string based on a positional relationship between the figure and the character string in the image.

Abstract: A nonvolatile memory device 1 capable of preventing interference between a read operation and a rewrite operation, and capable of preventing malfunctions that may occur in the event the read operation and the rewrite operation are performed simultaneously between memory blocks is provided. The nonvolatile memory device 1 is provided with a plurality of banks, a rewrite control unit 2 to which a first power source line VCC1 and a first ground line VSS1 are connected and which is adapted to control a rewrite operation with respect to a bank i, and a read control unit 5 to which a second power source line VCC2 and a second ground line VSS2 are connected and which is adapted to control a read operation with respect to a bank j, wherein the rewrite control unit 2 and the read control unit 5 are arranged so as to be spaced from each another.

Abstract: In the storage device of the invention, latch control is performed on a series of signals in response to latch control signals. Latch control terminals are provided to which the latch control signals are input respectively and a plurality of signal terminals to which a series of signals are input. Herein, a plurality of latch circuits is provided so as to correspond to the plurality of signal terminals, respectively. The plurality of latch circuits are located within a specified distance from their associated signal terminals respectively and within a specified distance from the latch control terminals. The delays of signal transmission from the signal terminals to their associated latch circuits can be equalized and the delays of signal transmission from the latch control terminals to which the latch control signals for executing latch control are input to the latch circuits can be equalized. This contributes to a reduction in the skew of the latch characteristics of the signals.

Abstract: In the storage device of the invention, latch control is performed on a series of signals in response to latch control signals. Latch control terminals are provided to which the latch control signals are input respectively and a plurality of signal terminals to which a series of signals are input. Herein, a plurality of latch circuits is provided so as to correspond to the plurality of signal terminals, respectively. The plurality of latch circuits are located within a specified distance from their associated signal terminals respectively and within a specified distance from the latch control terminals. The delays of signal transmission from the signal terminals to their associated latch circuits can be equalized and the delays of signal transmission from the latch control terminals to which the latch control signals for executing latch control are input to the latch circuits can be equalized. This contributes to a reduction in the skew of the latch characteristics of the signals.

Abstract: In the storage device of the invention, latch control is performed on a series of signals in response to latch control signals. Latch control terminals are provided to which the latch control signals are input respectively and a plurality of signal terminals to which a series of signals are input. Herein, a plurality of latch circuits is provided so as to correspond to the plurality of signal terminals, respectively. The plurality of latch circuits are located within a specified distance from their associated signal terminals respectively and within a specified distance from the latch control terminals. The delays of signal transmission from the signal terminals to their associated latch circuits can be equalized and the delays of signal transmission from the latch control terminals to which the latch control signals for executing latch control are input to the latch circuits can be equalized. This contributes to a reduction in the skew of the latch characteristics of the signals.

Abstract: A nonvolatile memory device 1 capable of preventing interference between a read operation and a rewrite operation, and capable of preventing malfunctions that may occur in the event the read operation and the rewrite operation are performed simultaneously between memory blocks is provided. The nonvolatile memory device 1 is provided with a plurality of banks, a rewrite control unit 2 to which a first power source line VCC1 and a first ground line VSS1 are connected and which is adapted to control a rewrite operation with respect to a bank i, and a read control unit 5 to which a second power source line VCC2 and a second ground line VSS2 are connected and which is adapted to control a read operation with respect to a bank j, wherein the rewrite control unit 2 and the read control unit 5 are arranged so as to be spaced from each another.

Abstract: A nonvolatile memory device 1 capable of preventing interference between a read operation and a rewrite operation, and capable of preventing malfunctions that may occur in the event the read operation and the rewrite operation are performed simultaneously between memory blocks is provided. The nonvolatile memory device 1 is provided with a plurality of banks, a rewrite control unit 2 to which a first power source line VCC1 and a first ground line VSS1 are connected and which is adapted to control a rewrite operation with respect to a bank i, and a read control unit 5 to which a second power source line VCC2 and a second ground line VSS2 are connected and which is adapted to control a read operation with respect to a bank j, wherein the rewrite control unit 2 and the read control unit 5 are arranged so as to be spaced from each another.

Abstract: A semiconductor device (1) is provided which includes a regular cell array unit (30), a redundant cell array unit (31) that is provided in relation to the regular cell array unit (30), and a PGM/ER state machine (20) that controls reprogramming in which, when programming of a sector in the regular cell array unit fails (step S3), data involved in the programming that fails and data already stored in the sector in the regular cell array unit are written (step S8) into the redundant cell array unit (31). Since reprogramming is performed to write the data already written in the sector as well as the data involved in the programming that fails into the redundant cell array unit (31), data loss can be prevented and data can be secured, thereby increasing the reliability of the system.

Abstract: In the storage device of the invention, latch control is performed on a series of signals in response to latch control signals. Latch control terminals are provided to which the latch control signals are input respectively and a plurality of signal terminals to which a series of signals are input. Herein, a plurality of latch circuits is provided so as to correspond to the plurality of signal terminals, respectively. The plurality of latch circuits are located within a specified distance from their associated signal terminals respectively and within a specified distance from the latch control terminals. The delays of signal transmission from the signal terminals to their associated latch circuits can be equalized and the delays of signal transmission from the latch control terminals to which the latch control signals for executing latch control are input to the latch circuits can be equalized. This contributes to a reduction in the skew of the latch characteristics of the signals.

Abstract: A nonvolatile memory device 1 capable of preventing interference between a read operation and a rewrite operation, and capable of preventing malfunctions that may occur in the event the read operation and the rewrite operation are performed simultaneously between memory blocks is provided. The nonvolatile memory device 1 is provided with a plurality of banks, a rewrite control unit 2 to which a first power source line VCC1 and a first ground line VSS1 are connected and which is adapted to control a rewrite operation with respect to a bank i, and a read control unit 5 to which a second power source line VCC2 and a second ground line VSS2 are connected and which is adapted to control a read operation with respect to a bank j, wherein the rewrite control unit 2 and the read control unit 5 are arranged so as to be spaced from each another.

Abstract: A semiconductor device (1) is provided which includes a regular cell array unit (30), a redundant cell array unit (31) that is provided in relation to the regular cell array unit (30), and a PGM/ER state machine (20) that controls reprogramming in which, when programming of a sector in the regular cell array unit fails (step S3), data involved in the programming that fails and data already stored in the sector in the regular cell array unit are written (step S8) into the redundant cell array unit (31). Since reprogramming is performed to write the data already written in the sector as well as the data involved in the programming that fails into the redundant cell array unit (31), data loss can be prevented and data can be secured, thereby increasing the reliability of the system.

Abstract: The present invention is a memory circuit, comprises: a memory cell array including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells disposed in the positions of intersection between the bit lines and the word lines; and a page buffer, which is connected to the bit line and which detects memory cell data by judging with predetermined sense timing the potential of the bit line when a pre-charged bit line potential is discharged in accordance to a cell current of a selected memory cell. Further the sense timing differs in accordance with the position of the selected memory cell in the memory cell array.

Abstract: The present invention is a memory circuit, comprises: a memory cell array including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells disposed in the positions of intersection between the bit lines and the word lines; and a page buffer, which is connected to the bit line and which detects memory cell data by judging with predetermined sense timing the potential of the bit line when a pre-charged bit line potential is discharged in accordance to a cell current of a selected memory cell. Further the sense timing differs in accordance with the position of the selected memory cell in the memory cell array.

Abstract: A communication controlling apparatus, which is connected to a telephone line and a serial bus, comprises a mapping table, which brings a fixed address, which a terminal device possesses, into correspondence with a node ID assigned to a terminal device connected to the current serial bus. Then, the node ID of the terminal device, serving as a recipient of data received from the telephone line, is obtained from the mapping table, and the received data from the line is transmitted to the terminal device via the serial bus using the obtained node ID.

Abstract: A semiconductor integrated circuit device is intended to prevent generation of an unnecessary leak current and hence to reduce power consumption.

Abstract: A semiconductor memory device has an oscillator unit for generating refresh pulses, a refresh address detection unit for detecting refreshed addresses and outputting a predetermined signal upon the completion of the refreshing of all addresses, and an output control unit for continuing a self-refresh mode to refresh all addresses according to the signal from the refresh address detection unit, before releasing the self-refresh mode in response to an external signal. Therefore, the refresh operation is continued until all cells are refreshed, thereby data stored in the semiconductor memory device is not lost and is correctly refreshed.