Patents by Inventor Makoto Oyamada

Makoto Oyamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8609918
    Abstract: This invention relates to a method of efficiently producing a high-purity para-substituted aromatic hydrocarbon while suppressing caulking without requiring isomerization-adsorption separation steps, and more particularly to a method of producing a para-substituted aromatic hydrocarbon, characterized in that a methylating agent and an aromatic hydrocarbon are reacted in the presence of a catalyst formed by coating MFI type zeolite having a particle size of not more than 100 ?m with a crystalline silicate.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: December 17, 2013
    Assignee: JX Nippon Oil & Energy Corporation
    Inventors: Koichi Matsushita, Chikanori Nakaoka, Naoharu Igarashi, Makoto Oyamada
  • Publication number: 20110009682
    Abstract: This invention relates to a method of efficiently producing a high-purity para-substituted aromatic hydrocarbon while suppressing caulking without requiring isomerization-adsorption separation steps, and more particularly to a method of producing a para-substituted aromatic hydrocarbon, characterized in that a methylating agent and an aromatic hydrocarbon are reacted in the presence of a catalyst formed by coating MFI type zeolite having a particle size of not more than 100 ?m with a crystalline silicate.
    Type: Application
    Filed: March 26, 2009
    Publication date: January 13, 2011
    Applicant: JX NIPPON OIL & ENERGY CORPORATION
    Inventors: Koichi Matsushita, Chikanori Nakaoka, Naoharu Igarashi, Makoto Oyamada
  • Patent number: 7285451
    Abstract: To reduce variation in channel lengths of MOS transistors within a circuit functional module. When exposure of a wafer substrate having a semiconductor integrated circuit device 1 including a plurality of CMOS circuit module regions CCM11 to CCM22 to be subject to substrate bias control formed in a core region 10 is performed using a step-and-scan type projection exposure apparatus, scanning is performed in the same direction as a longitudinal direction of the respective CMOS circuit module regions CCM11 to CCM22. In this device, a gate insulating film is formed on the substrate, a gate electrode material film is formed on the gate insulating film, and a photoresist film is formed on the gate electrode material film.
    Type: Grant
    Filed: April 13, 2006
    Date of Patent: October 23, 2007
    Assignee: NEC Electronics Corporation
    Inventor: Makoto Oyamada
  • Publication number: 20060232300
    Abstract: To reduce variation in channel lengths of MOS transistors within a circuit functional module. When exposure of a wafer substrate having a semiconductor integrated circuit device 1 including a plurality of CMOS circuit module regions CCM11 to CCM22 to be subject to substrate bias control formed in a core region 10 is performed using a step-and-scan type projection exposure apparatus, scanning is performed in the same direction as a longitudinal direction of the respective CMOS circuit module regions CCM11 to CCM22. In this device, a gate insulating film is formed on the substrate, a gate electrode material film is formed on the gate insulating film, and a photoresist film is formed on the gate electrode material film.
    Type: Application
    Filed: April 13, 2006
    Publication date: October 19, 2006
    Inventor: Makoto Oyamada