Abstract: A power conversion system according to the present disclosure includes a plurality of power converters for performing power conversion on AC power and is connected to a power grid of multi-phase power that is a combination of multiple alternating current sources with mutually different phases. Each of the plurality of power converters includes a power converter circuit, a setting unit, and a control circuit. The power converter circuit performs power conversion between either DC power or AC power and AC power supplied from any of the multiple alternating current sources. The setting unit selects one of the multiple alternating current sources as a target of the power conversion to be performed by the power converter circuit. The control circuit controls operation of the power converter circuit in accordance with selection made by the setting unit.

Abstract: A power conversion system according to the present disclosure includes a plurality of power converters for performing power conversion on AC power and is connected to a power grid of multi-phase power that is a combination of multiple alternating current sources with mutually different phases. Each of the plurality of power converters includes a power converter circuit, a setting unit, and a control circuit. The power converter circuit performs power conversion between either DC power or AC power and AC power supplied from any of the multiple alternating current sources. The setting unit selects one of the multiple alternating current sources as a target of the power conversion to be performed by the power converter circuit. The control circuit controls operation of the power converter circuit in accordance with selection made by the setting unit.

Abstract: A control unit controls an inverter circuit such that a positive voltage and a negative voltage are alternately applied to a primary winding. The control unit controls a cycloconverter so as to allow no power to be transmitted between the cycloconverter and the inverter circuit in a first period including an inversion period during which a voltage of the primary winding has its polarity inverted. The control unit also controls the cycloconverter so as to allow power to be transmitted either in a first direction from the cycloconverter toward the inverter circuit, or in a second direction opposite from the first direction, in a second period different from the first period.

Abstract: The control unit controls the converter unit not to cause transfer of power between the transformer circuit unit and the converter unit in the first time period including the reversal time period in which a reversal of polarity of the voltage across the primary winding occurs. The control unit controls the converter unit to cause transfer of power in the first direction from the transformer circuit unit to the converter unit or the second direction opposite to the first direction in the second time period different from the first time period.

Abstract: A power conversion system includes a first capacitor, an isolated type converter circuit, and a control circuit. The first capacitor is connected to the direct-current power supply via an inrush current prevention circuit. The inrush current prevention circuit is switchable at least between a high-impedance state and a low-impedance state. The converter circuit includes a transformer, and the first capacitor is connected to a primary winding wire of the transformer. The control circuit controls the inrush current prevention circuit and the converter circuit to cause the converter circuit to start operating, and then, the control circuit switches the inrush current prevention circuit from the high-impedance state to the low-impedance state.

Abstract: A power conversion system includes a first capacitor, an isolated type converter circuit, and a control circuit. The first capacitor is connected to the direct-current power supply via an inrush current prevention circuit. The inrush current prevention circuit is switchable at least between a high-impedance state and a low-impedance state. The converter circuit includes a transformer, and the first capacitor is connected to a primary winding wire of the transformer. The control circuit controls the inrush current prevention circuit and the converter circuit to cause the converter circuit to start operating, and then, the control circuit switches the inrush current prevention circuit from the high-impedance state to the low-impedance state.

Abstract: The control unit controls the converter unit not to cause transfer of power between the transformer circuit unit and the converter unit in the first time period including the reversal time period in which a reversal of polarity of the voltage across the primary winding occurs. The control unit controls the converter unit to cause transfer of power in the first direction from the transformer circuit unit to the converter unit or the second direction opposite to the first direction in the second time period different from the first time period.

Abstract: A control unit controls an inverter circuit such that a positive voltage and a negative voltage are alternately applied to a primary winding. The control unit controls a cycloconverter so as to allow no power to be transmitted between the cycloconverter and the inverter circuit in a first period including an inversion period during which a voltage of the primary winding has its polarity inverted. The control unit also controls the cycloconverter so as to allow power to be transmitted either in a first direction from the cycloconverter toward the inverter circuit, or in a second direction opposite from the first direction, in a second period different from the first period.

Abstract: A reconfigurable circuit of reduced circuit scale. The reconfigurable circuit of the present invention comprises a plurality of ALUs capable of changing functions. The plurality of ALUs are arranged in a matrix. At least one connection unit capable of establishing connection between the ALUs selectively is provided between the stages of the ALUs. This connection unit is not intended to allow connection between all the logic circuits in adjoining stages, but is configured so that the logic circuits are each connectable with only some of the logic circuits pertaining to the other stages. The connection limitation allows a reduction in circuit scale.

Abstract: A data flow graph processing method divides a program describing target operations into two or more subprograms and converts each of the two or more subprograms into a data flow graph (DFG) representing dependency in execution between operations carried out in sequence. Also generated is flow data indicating the order of execution of DFGs corresponding to respective subprograms. DFGs are converted into configuration data and the flow data is converted into control data.

Abstract: A data flow graph processing method divides at least one DFG generated into a plurality of sub-DFGs, in accordance with the number of logic circuits in a circuit set in a reconfigurable circuit. When the reconfigurable circuit is provided with a structure including multiple-row connections, the number of columns in the sub-DFG is configured to be equal to or fewer than the number of logic circuits per row in the reconfigurable circuit. Subsequently, the sub-DFGs are joined so as to generate a joined DFG. The number of columns in the joined DFG is also configured to be equal to or fewer than the number of columns per row in the reconfigurable circuit. The joined DFG is redivided to sizes with number of rows equal to or fewer than the number of rows in the reconfigurable circuit, so as to generate subjoined DFGs mappable into the reconfigurable circuit.

Abstract: A processing circuit according to the present invention includes a plurality of logic circuits (designated as L11, . . . , and L44) formed by arranging in arrays and is configured to input an output from a logic circuit to the logic circuit located on the following row. Each of the plurality of logic circuits includes an operation circuit (ALU) configured to perform an operation on inputted data; and a selecting unit (MUX) configured to select and output any one of an operation output from the operation circuit or an operation output from the logic circuit located on the preceding row.

Abstract: In the processing device in accordance with the present invention, a plurality of divided circuits obtained by dividing one circuit are successively configured on a reconfigurable circuit, an operation is executed by the divided circuits by feeding back an output of one divided circuit to a next divided circuit, and an output is taken out from the last configured divided circuit. As a feedback path, a path portion is formed, which connects the output of the reconfigurable circuit to its input. By successively configuring the divided circuits, one circuit as a whole can be implemented.

Abstract: A data flow graph processing method divides a program describing target operations into two or more subprograms and converts each of the two or more subprograms into a data flow graph (DFG) representing dependency in execution between operations carried out in sequence. Also generated is flow data indicating the order of execution of DFGs corresponding to respective subprograms. DFGs are converted into configuration data and the flow data is converted into control data.

Abstract: A data flow graph processing method divides at least one DFG generated into a plurality of sub-DFGs, in accordance with the number of logic circuits in a circuit set in a reconfigurable circuit. When the reconfigurable circuit is provided with a structure including multiple-row connections, the number of columns in the sub-DFG is configured to be equal to or fewer than the number of logic circuits per row in the reconfigurable circuit. Subsequently, the sub-DFGs are joined so as to generate a joined DFG. The number of columns in the joined DFG is also configured to be equal to or fewer than the number of columns per row in the reconfigurable circuit. The joined DFG is redivided to sizes with number of rows equal to or fewer than the number of rows in the reconfigurable circuit, so as to generate subjoined DFGs mappable into the reconfigurable circuit.

Abstract: A reconfigurable circuit of reduced circuit scale. The reconfigurable circuit of the present invention comprises a plurality of ALUs capable of changing functions. The plurality of ALUs are arranged in a matrix. At least one connection unit capable of establishing connection between the ALUs selectively is provided between the stages of the ALUs. This connection unit is not intended to allow connection between all the logic circuits in adjoining stages, but is configured so that the logic circuits are each connectable with only some of the logic circuits pertaining to the other stages. The connection limitation allows a reduction in circuit scale.