Abstract: A semiconductor device 1 includes: a split-gate transistor 9 connected between a drain electrode 11 (output electrode OUT) and a ground electrode and having a plurality of individually controllable channel regions; an active clamp circuit 26 configured to limit the output voltage VOUT appearing at the output electrode 11 to a clamp voltage or below; and a gate control circuit 25 configured to raise the ON resistance of the split-gate transistor 9 gently (or stepwise) after the split-gate transistor is switched from the ON state to the OFF state before the active clamp circuit 26 limits the output voltage VOUT.

Abstract: A semiconductor device includes: a first output transistor and a second output transistor configured to be connected between a first terminal and second terminal; an active clamp circuit configured to be connected to a first control terminal of the first output transistor to limit a terminal-to-terminal voltage appearing between the first and second terminals to a clamp voltage or less; a first variable resistive element provided between a node configured to be fed with a control signal and the first control terminal; a second variable resistive element provided between the node and a second control terminal of the second output transistor; and a turn-off circuit configured to be connected to a connection node between the second variable resistive element and the second control terminal so as to be able to turn the second output transistor off.