Abstract: The disclosure provides a semiconductor storage device and a reading method, which may achieve high-speed processing time for error detection and correction and achieve miniaturization. The flash memory of the disclosure has a NAND chip and an ECC chip. The NAND chip has: a memory array; a page buffer/sensing circuit, including latches L1 and L2; and dedicated input and output terminals, which may be used for data transmission with ECC chip. The latch L1 contains cache C0 and cache C1, and the latch L2 only contains the cache C1. The data in the cache C0 of the latch L1 and the data in the cache C1 of the latch L2 are transmitted to the ECC chip. In response to outputting data at the initial address from the ECC chip, the next page is read from the memory array, and the read data is held in the latch L1.

Abstract: The disclosure provides a semiconductor device and a reading method capable of achieving high-speed reading performance. A NAND flash memory according to the disclosure includes: a bit line selection circuit for selecting an even-numbered bit line or an odd-numbered bit line, and a page buffer/reading circuit connected to the bit line selection circuit. A reading method of a flash memory includes: precharging the selected bit line with a virtual power supply (VIRPWR) connected to the bit line selection circuit (step #1); and initializing a latch circuit (L1) through a voltage supply node V1 in parallel with the precharging of the selected bit line (step #1_2); and initializing the page buffer/reading circuit 170 through the voltage supply node V1 (step #1_3).

Abstract: The disclosure provides a semiconductor storage device and a reading method that can achieve high-speed processing of error detection and correction and miniaturization. The flash memory of the disclosure has a NAND chip and an ECC chip. The NAND chip includes a memory array, and a page buffer/sensing circuit including a latch (L1) and a latch (L2). The ECC chip includes RAM_E and RAM_O. The RAM_E and RAM_O hold the read data output from the latches (L1, L2) of the NAND chip. RAM_E holds the data of the even-numbered sectors, and RAM_O holds the data of the odd-numbered sectors. Making RAM_E or RAM_O alternately hold the data of the sectors can reduce the data size of RAM_E and RAM_O.

Abstract: A semiconductor apparatus implementing a high speed data output and compensating a resetting of a latch circuit is provided. A readout method of a NAND type flash memory includes: a pre-charging step performing a pre-charging on a bit line and a NAND string connected to the bit line through a sense node (SNS); a resetting step performing a resetting on the latch circuit after the pre-charging; and a discharging step performing a discharging on the NAND string after the resetting.

Abstract: A continuous readout method of a flash memory is provided. Selected bit lines (BL0, BL4, BL8, and BL12) are masked by three non-selected bit lines when data of a cache memory (C0) of a selected page of a memory cell array is read. Selected bit lines (BL2, BL6, BL10, and BL14) are masked by three non-selected bit lines when data of a cache memory (C1) of the same selected page is read. In this way, each of first page data and second page data read from a plurality of selected pages is continuously outputted.

Abstract: The disclosure provides a semiconductor storage device and a reading method, which may achieve high-speed processing time for error detection and correction and achieve miniaturization. The flash memory of the disclosure has a NAND chip and an ECC chip. The NAND chip has: a memory array; a page buffer/sensing circuit, including latches L1 and L2 ; and dedicated input and output terminals, which may be used for data transmission with ECC chip. The latch L1 contains cache C0 and cache C1, and the latch L2 only contains the cache C1. The data in the cache C0 of the latch L1 and the data in the cache C1 of the latch L2 are transmitted to the ECC chip. In response to outputting data at the initial address from the ECC chip, the next page is read from the memory array, and the read data is held in the latch L1.

Abstract: The disclosure provides a semiconductor storage device and a reading method that can achieve high-speed processing of error detection and correction and miniaturization. The flash memory of the disclosure has a NAND chip and an ECC chip. The NAND chip includes a memory array, and a page buffer/sensing circuit including a latch (L1) and a latch (L2). The ECC chip includes RAM_E and RAM_O. The RAM_E and RAM_O hold the read data output from the latches (L1, L2) of the NAND chip. RAM_E holds the data of the even-numbered sectors, and RAM_O holds the data of the odd-numbered sectors. Making RAM_E or RAM_O alternately hold the data of the sectors can reduce the data size of RAM_E and RAM_O.

Abstract: The disclosure provides a semiconductor storage device, which can shorten the processing time for error detection and correction. The flash memory of the present disclosure has a NAND chip and an ECC chip. The NAND chip has dedicated input and output terminals which can transmit data with the ECC chip, and the ECC chip has a dedicated input and output terminal which can transmit data with the NAND chip. When reading in the NAND chip, the NAND chip transmits the read data containing the parity data to the ECC chip through the dedicated input and output terminals. The ECC chip detect and correct errors in the read data based on the parity data, and the corrected data is transmitted to the controller through the input and output terminals.

Abstract: A semiconductor memory device and an operation method capable of suppressing malfunctions and the like and performing safe operations are provided. A flash memory of the disclosure includes a controller which controls an operation based on a code read from a ROM. The operation method of the disclosure includes detecting whether the code read from the ROM has an error by a CRC processing unit; determining whether to transition to a safe mode when the code having the error is detected; and detecting and correcting the error of the code by an ECC processing unit after transitioning to the safe mode.

Abstract: A semiconductor device that can compensate for threshold fluctuations in memory cells using capacitive coupling. The flash memory includes a NAND-type memory cell array, a programing device, a reading device, and an offset voltage determining unit. The programing device programs the memory cells connected to a selected word line. The reading device reads the memory cells connected to a selected word line. The programing device programs the memory cells of a monitoring NAND string simultaneously when programing a word line. The reading device comprises a current detecting unit applying a read voltage to an unselected word line n+1, and detecting the current of the monitoring NAND string. The offset voltage determining unit determines the first and second offset voltage based on the detected current, and a reading pass voltage is applied to the unselected word line, a read voltage is applied to the selected word line.

Abstract: A semiconductor storing apparatus capable of shortening a ECC processing time of a readout operation is provided, including a flash memory includes: a memory cell array; a page buffer/sense circuit holding data read out from a selected page of the memory cell array; an error correcting code circuit receiving data from the page buffer/sense circuit and holding error address information of the data; an output circuit selecting data from the page buffer/sense circuit based on a column address, and outputting the selected data to a data bus; and an error correction part correcting data of the data bus based on the error address information.

Abstract: A semiconductor device capable of performing high-speed read or high-reliability read is provided. A reading method of a NAND flash memory includes: pre-charging a sensing node through a voltage-supply node; discharging the sensing node to the voltage-supply node for a prescribed operation; recharging the sensing node by the voltage-supply node after the prescribed operation; and discharging a NAND string and sensing a memory cell.

Abstract: The disclosure provides a semiconductor device and a reading method capable of achieving high-speed reading performance. A NAND flash memory according to the disclosure includes: a bit line selection circuit for selecting an even-numbered bit line or an odd-numbered bit line, and a page buffer/reading circuit connected to the bit line selection circuit. A reading method of a flash memory includes: precharging the selected bit line with a virtual power supply (VIRPWR) connected to the bit line selection circuit (step #1); and initializing a latch circuit (L1) through a voltage supply node V1 in parallel with the precharging of the selected bit line (step #1_2); and initializing the page buffer/reading circuit 170 through the voltage supply node V1 (step #1_3).

Abstract: A flash memory including a NAND memory cell array, a current detection unit, an offset voltage determining unit, and a reading voltage generating unit. The NAND memory cell array forms at least one monitoring NAND string in each block, which are used to monitor the cycle frequency of programing and erasing. The current detection unit detects the current that flows through the monitoring NAND string. The offset voltage determining unit determines the first offset voltage and the second offset voltage that are respectively added to the read-pass voltage and the reading voltage, according to the current detected. The reading voltage generating unit generates the read-pass voltage with the first offset voltage added. The reading voltage generating unit also generates the reading voltage with the second offset voltage added.

Abstract: A semiconductor apparatus and a continuous readout method for improving prior continuous readout are provided. A flash memory includes: a NAND memory cell array, an input/output circuit, an ECC circuit, a controller, a word-line selection circuit, a page buffer/readout circuit, and a row selection circuit. When performing the continuous readout of pages, the controller performs an array readout of a first half page of a selection page on the memory cell array and an array readout of a second half page of the selection page on the memory cell array independently, and continuously outputs the respectively read data of the half pages in synchronization with a clock signal.

Abstract: A continuous reading method of a flash memory is provided, including: after outputting data held in a cache memory (C0) of a latch (L1) of a page buffer/sensing circuit, data of the cache memory (C0) of a next page is read from a memory cell array, and the read data of the cache memory (C0) is held in the latch (L1). After outputting data held in the cache memory (C1) of the latch (L1), data of the same next page of the cache memory (C1) is read from the memory cell array, and the read data of the cache memory (C1) is held in the latch (L1).

Abstract: A semiconductor device capable of performing high-speed read or high-reliability read is provided. A reading method of a NAND flash memory includes: pre-charging a sensing node through a voltage-supply node; discharging the sensing node to the voltage-supply node for a prescribed operation; recharging the sensing node by the voltage-supply node after the prescribed operation; and discharging a NAND string and sensing a memory cell.

Abstract: A semiconductor device that can compensate for threshold fluctuations in memory cells using capacitive coupling. The flash memory includes a NAND-type memory cell array, a programing device, a reading device, and an offset voltage determining unit. The programing device programs the memory cells connected to a selected word line. The reading device reads the memory cells connected to a selected word line. The programing device programs the memory cells of a monitoring NAND string simultaneously when programing a word line. The reading device comprises a current detecting unit applying a read voltage to an unselected word line n+1, and to detecting the current of the monitoring NAND string. The offset voltage determining unit determines the first and second offset voltage based on the detected current, and a reading pass voltage is applied to the unselected word line, a read voltage is applied to the selected word line.

Abstract: A flash memory including a NAND memory cell array, a current detection unit, an offset voltage determining unit, and a reading voltage generating unit. The NAND memory cell array forms at least one monitoring NAND string in each block, which are used to monitor the cycle frequency of programing and erasing. The current detection unit detects the current that flows through the monitoring NAND string. The offset voltage determining unit determines the first offset voltage and the second offset voltage that are respectively added to the read-pass voltage and the reading voltage, according to the current detected. The reading voltage generating unit generates the read-pass voltage with the first offset voltage added. The reading voltage generating unit also generates the reading voltage with the second offset voltage added.

Abstract: A semiconductor apparatus implementing a high speed data output and compensating a resetting of a latch circuit is provided. A readout method of a NAND type flash memory includes: a pre-charging step performing a pre-charging on a bit line and a NAND string connected to the bit line through a sense node (SNS); a resetting step performing a resetting on the latch circuit after the pre-charging; and a discharging step performing a discharging on the NAND string after the resetting.