Patents by Inventor Makoto Shuto

Makoto Shuto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10267834
    Abstract: There is a need for high-order frequency measurement without greatly increasing consumption currents and chip die sizes. A semiconductor device includes: an electric power measuring portion that performs electric power measurement; a high-order frequency measuring portion that performs high-order frequency measurement; and a clock controller that supplies an electric power measuring portion with a first clock signal at a first sampling frequency and supplies a high-order frequency measuring portion with a second clock signal at a second sampling frequency. The second sampling frequency is higher than the first sampling frequency.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: April 23, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Makoto Shuto, Kazuyoshi Kawai, Mitsuya Fukazawa, Robert Nolf, Robert Dalby
  • Publication number: 20180143229
    Abstract: There is a need for high-order frequency measurement without greatly increasing consumption currents and chip die sizes. A semiconductor device includes: an electric power measuring portion that performs electric power measurement; a high-order frequency measuring portion that performs high-order frequency measurement; and a clock controller that supplies an electric power measuring portion with a first clock signal at a first sampling frequency and supplies a high-order frequency measuring portion with a second clock signal at a second sampling frequency. The second sampling frequency is higher than the first sampling frequency.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 24, 2018
    Applicant: Renesas Electronics Corporation
    Inventors: Makoto SHUTO, Kazuyoshi KAWAI, Mitsuya FUKAZAWA, Robert NOLF, Robert DALBY
  • Publication number: 20060242385
    Abstract: Disclosed is a technology of generating an instruction set architecture (hereinafter, referred to as ‘ISA’) and a series of logic circuit configuration information of a processor for executing an application program from an application program described in a high-level language. The present invention also relates to a custom LSI development platform technology which can design, develop, and manufacture the application specific custom LSI in a short time by applying the generated ISA and logic circuit configuration information to a dynamic logic circuit reconfigurable processor. Furthermore, disclosed is a dynamically reconfigurable processor, which is reconfigurable using the generated logic circuit configuration information. Associated methods are also disclosed.
    Type: Application
    Filed: November 4, 2005
    Publication date: October 26, 2006
    Inventors: Kazuaki Murakami, Makoto Shuto, Lovic Gauthier, Takuma Matsuo, Tetsuya Hasebe, Shuichi Kikuchi