Abstract: A motion state monitoring system, a training support system, a motion state monitoring method, and a program capable of suitably managing measurement results according to an attaching direction of a sensor are provided. A motion state monitoring system according to the present disclosure monitors a motion state of a target part of a subject's body. The motion state monitoring system includes an acquisition unit, an attaching direction detection unit, and a control processing unit. The acquisition unit acquires sensing information of a sensor attached to the target part. The attaching direction detection unit detects an attaching direction of the sensor. The control processing unit outputs information related to the sensing information in association with the attaching direction.

Abstract: A processor includes a controller that measures an error rate of a signal that propagates through a communication line; switches to use a spare line to perform a first communication when a first error rate of a signal that propagates through a first communication line of a first line group exceeds a first threshold, the first communication being performed using the first communication line; and switches to use the first communication line to perform the first communication and switches to use the spare line to perform a second communication when the first communication is performed using the spare line, when a second error rate of a signal that propagates through a second communication line of a second line group exceeds a second threshold higher than the first threshold, and when the first error rate is lower than the second threshold; and a processor core that exchanges information via the controller.

Abstract: A processor includes a controller that measures an error rate of a signal that propagates through a communication line; switches to use a spare line to perform a first communication when a first error rate of a signal that propagates through a first communication line of a first line group exceeds a first threshold, the first communication being performed using the first communication line; and switches to use the first communication line to perform the first communication and switches to use the spare line to perform a second communication when the first communication is performed using the spare line, when a second error rate of a signal that propagates through a second communication line of a second line group exceeds a second threshold higher than the first threshold, and when the first error rate is lower than the second threshold; and a processor core that exchanges information via the controller.

Abstract: The arithmetic processing device includes a first memory control unit configured to control an access to a first memory, a second memory control unit configured to control an access to a second memory. The arithmetic processing device further includes a diagnostic control unit configured to sequentially diagnose parts within the first memory via the first memory control unit, and configured to sequentially store in the second memory via the second memory control unit, diagnostic results of sequentially diagnosing the parts in parallel with the diagnosing the parts via the first memory control unit.

Abstract: An apparatus includes a memory; and a processor that includes a memory-controller that controls transmission-and-reception of information to and from the memory, wherein the memory-controller comprises a buffer that includes storage-regions, a control-circuit that stores, in one of the storage-regions, information that operates the memory among pieces of information transmitted to the memory, a counter that counts a number of pieces of second information transmitted to the memory, the second information being information transmitted to the memory since the information is transmitted to the memory until the next information is transmitted to the memory and indicating no-transmission of the information, a second buffer that includes a second storage-regions respectively corresponding to the storage-regions, and a second control-circuit that stores a count value of the counter in one of the second storage-regions in association with the information stored in the storage region.

Abstract: An arithmetic processing unit including a memory controller configured to make variable-length access requests allowing a plurality of lengths to a memory, the memory controller comprising: a plurality of buffers configured to hold the access requests for each of the lengths of the access requests; and an arbitrator configured to select one of access requests stored in the plurality of buffers in accordance with a number of remaining resources of the memory.

Abstract: A memory controller has a request holding unit holding a write request and a read request; a transmission unit transmitting any one of the write request and the read request to a memory through a transmission bus; a reception unit receiving read data corresponding to the read request through a reception bus; and a request arbitration unit performing: a first processing of transmitting the write request before the read request, when a first reception time is not later than a second reception time, and a second processing of transmitting the read request before the write request, when the first reception time is later than the second reception time. The first reception time is when reception of the read data is started when the write request is transmitted first, and the second reception time is when the reception of the read data is started when the read request is transmitted first.

Abstract: An arithmetic processing device which connects to a main memory, the arithmetic processor includes a cache memory which stores data, an arithmetic unit which performs an arithmetic operation for data stored in the cache memory, a first control device which controls the cache memory and outputs a first request which reads the data stored in the main memory, and a second control device which is connected to the main memory and transmits a plurality of second requests which are divided the first request output from the first control device, receives data corresponding to the plurality of second requests which is transmitted from the main memory and sends each of the data to the first control device.

Abstract: The information processing apparatus includes an arithmetic processing device configured to output an access request, a storage device configured to store data, a storage control device configured to accept the access request to the storage device from the arithmetic processing device, transfer the accepted access request to the storage device, and acquire a response to the access request from the storage device, and a diagnosis control device configured to send an access request to the storage device to the storage control device in place of the access request to the storage device from the arithmetic processing device, and acquire a response from the storage device via the storage control device.

Abstract: A memory controller is provided between a CPU and a main memory, controls access from the CPU to the main memory, and includes a data storage area and a controller. In a case where error information indicating that an error occurs is included in write data from the CPU to the main memory, the controller stores the write data in a data storage area in association with a writing destination address. Therefore, even in a case where the error information is not written in the main memory, the error information can be recorded.

Abstract: The arithmetic processing device includes a first memory control unit configured to control an access to a first memory, a second memory control unit configured to control an access to a second memory. The arithmetic processing device further includes a diagnostic control unit configured to sequentially diagnose parts within the first memory via the first memory control unit, and configured to sequentially store in the second memory via the second memory control unit, diagnostic results of sequentially diagnosing the parts in parallel with the diagnosing the parts via the first memory control unit.

Abstract: The information processing apparatus includes an arithmetic processing device configured to output an access request, a storage device configured to store data, a storage control device configured to accept the access request to the storage device from the arithmetic processing device, transfer the accepted access request to the storage device, and acquire a response to the access request from the storage device, and a diagnosis control device configured to send an access request to the storage device to the storage control device in place of the access request to the storage device from the arithmetic processing device, and acquire a response from the storage device via the storage control device.

Abstract: An information processor apparatus includes: a storage device to perform processing based on a read request or a write request and output a response after completing the processing; an arithmetic processor to output the read and write requests to the storage device; and a control device, including paths, to control the storage device; the control device: receives the read request or the write request from the arithmetic processor; acquires, for each of the paths, an overall time until the response to a transmitted read and write requests is received based on a first number of the transmitted read requests and a second number of the transmitted write requests, selects a used path based on the overall time; transmits the read request or the write request through the used path to the storage device; and receives the response to the read request or the write request through the used path.

Abstract: An arithmetic processing device which connects to a main memory, the arithmetic processor includes a cache memory which stores data, an arithmetic unit which performs an arithmetic operation for data stored in the cache memory, a first control device which controls the cache memory and outputs a first request which reads the data stored in the main memory, and a second control device which is connected to the main memory and transmits a plurality of second requests which are divided the first request output from the first control device, receives data corresponding to the plurality of second requests which is transmitted from the main memory and sends each of the data to the first control device.

Abstract: A memory controller has a request holding unit holding a write request and a read request; a transmission unit transmitting any one of the write request and the read request to a memory through a transmission bus; a reception unit receiving read data corresponding to the read request through a reception bus; and a request arbitration unit performing: a first processing of transmitting the write request before the read request, when a first reception time is not later than a second reception time, and a second processing of transmitting the read request before the write request, when the first reception time is later than the second reception time. The first reception time is when reception of the read data is started when the write request is transmitted first, and the second reception time is when the reception of the read data is started when the read request is transmitted first.

Abstract: An arithmetic processing device promotes transmission efficiency between a processor and a memory. The arithmetic processing device has an arithmetic processing unit which issues an instruction accompanying with data which is sent to the memory, a judgment unit which judges whether or not a redundancy degree of the data which is accompanied with the instruction is more than a predetermined value, a compression unit which judges whether or not compress the data based on an waiting time and a compression time when the redundancy degree of the data is more than the predetermined value, and compress the data when judging that performs the compression, and an instruction arbitration unit which transfers the instruction accompanying with the compressed data to the memory when the compression unit performs the compression and transfers the instruction accompanying with the non-compressed data to the memory when the compression unit does not perform the compression.

Abstract: An arithmetic processing unit including a memory controller configured to make variable-length access requests allowing a plurality of lengths to a memory, the memory controller comprising: a plurality of buffers configured to hold the access requests for each of the lengths of the access requests; and an arbitrator configured to select one of access requests stored in the plurality of buffers in accordance with a number of remaining resources of the memory.

Abstract: A memory controller is provided between a CPU and a main memory, controls access from the CPU to the main memory, and includes a data storage area and a controller. In a case where error information indicating that an error occurs is included in write data from the CPU to the main memory, the controller stores the write data in a data storage area in association with a writing destination address. Therefore, even in a case where the error information is not written in the main memory, the error information can be recorded.

Abstract: An electric motor includes a housing that receives multiple magnets that are circumferentially arranged in the housing. A resilient member has two inserted portions that are respectively inserted into gaps formed among the magnets. For example, four inserted portions of the two resilient members are respectively inserted into four gaps formed among four magnets, so that the inserted portions are resiliently deformed in the gaps. The inserted portions apply force to the magnets such that the magnets are circumferentially spaced from each other. Thus, the four magnets are urged onto an inner wall of the housing by the two resilient members. As a result, movement of the magnets is restricted in both of the circumferential direction and the axial direction of the housing. Therefore, the magnets can be maintained in the housing using a simple structure without increasing the number of components.

Abstract: An electric motor includes a housing that receives multiple magnets that are circumferentially arranged in the housing. A resilient member has two inserted portions that are respectively inserted into gaps formed among the magnets. For example, four inserted portions of the two resilient members are respectively inserted into four gaps formed among four magnets, so that the inserted portions are resiliently deformed in the gaps. The inserted portions apply force to the magnets such that the magnets are circumferentially spaced from each other. Thus, the four magnets are urged onto an inner wall of the housing by the two resilient members. As a result, movement of the magnets is restricted in both of the circumferential direction and the axial direction of the housing. Therefore, the magnets can be maintained in the housing using a simple structure without increasing the number of components.