Abstract: A well region is provided on a doped semiconductor layer. A resistor element is formed on the well region and a fixed voltage level is applied. A parasitic capacitance is formed between the well region and the resistor and a noise generated at one end of the resistor is compensated for or filtered by the parasitic capacitance.

Abstract: In a level generating circuit 1 included in an internal power supply circuit of a DRAM, MOS transistors 14 and 16 for inactivating a V.sub.1 generating circuit 3, and MOS transistors 23 and 25 for inactivating a V.sub.2 generating circuit 5 are provided. When V.sub.1 is to be adjusted, V.sub.2 generating circuit 5 is inactivated, and when V.sub.2 is to be adjusted, V.sub.1 generating circuit 3 is inactivated. Therefore, failure of adjustment of internal power supply potential intVcc caused by confusion of V.sub.1 and V.sub.2 can be prevented.

Abstract: A semiconductor memory device 251 has a sense amplifier 7 of shared sense amplifier type. A switching signal generating circuit 253 is provided for application of control signals .phi..sub.1 and .phi..sub.2 to a control electrode of a connection transistor of sense amplifier 7. Switching signal generating circuit 253 applies control signals .phi..sub.1 and .phi..sub.2 which is boosted only for a prescribed time period after the rise of external /RAS signal to the control electrode of the connection transistor of sense amplifier 7. Therefore, as compared with the operation in which control signals .phi..sub.1 and .phi..sub.2 which are constantly boosted are applied, power consumption can be reduced.

Abstract: A semiconductor memory device includes a plurality of memory blocks, i main row or column select lines extending over the plurality of memory blocks, and a decoder for selecting one of the main row or column select lines in accordance with an applied address signal. The decoder includes i outputs. Each of the memory blocks includes a plurality of memory cells arranged in rows and columns and at least (i+1) sub row or column select lines each for selecting one row or one column of memory cells. A shift redundancy circuit is provided for each of the memory blocks, for connecting the main row or column select line and the sub row or column select line. The shift redundancy circuit includes a switch circuit for connecting one main row or column select line to one of the plurality of adjacent sub row or column select lines, and a circuit for setting a connection path of the switch circuit.

Abstract: In a general read out operation, data read out from a memory cell array is amplified by a preamplifier group. The amplified data is provided to a selector unit. The selector unit responds to a bit organization select signal to select data according to a predetermined bit configuration. The selected data is provided to a data bus. In a test mode, the selector unit responds to a test mode signal to provide a test result to a data bus corresponding to a predetermined bit organization. Therefore, only the required data bus is used according to the bit organization and the test mode.

Abstract: A semiconductor device according to the present invention includes on the main surface of a p substrate a storing circuit region and peripheral circuit regions. An n well surrounds a p well including the storing circuit region and a p well including the peripheral circuit regions. As a result, a capacitance element is formed in the semiconductor substrate. It is possible to miniaturize the semiconductor device, and to improve reliability of connection between elements.

Abstract: A semiconductor memory device includes a memory array. The bit line pairs of the odd number order in the memory array belong to a first group, and the bit line pairs of the even number order belong to a second group. A first amplifier is connected to each bit line pair. Corresponding to the first group, write buses read buses and a read/test circuit are provided. Corresponding to the second group, write buses read buses and a read/test circuit are provided. A column decoder selects a plurality of bit line pairs simultaneously at the time of testing. At the time of testing, each of the read/test circuits compares data read out from the plurality of bit line pairs belonging to the corresponding group with a given expected data for providing the comparison result.

Abstract: A plurality of sub chips are formed on a chip. An input/output buffer region is arranged around the plurality of sub chips. Each sub chip includes a sub chip control circuit region and a plurality of memory cell array blocks. Each memory cell array block includes a memory cell array region, a row decoder and control circuit region, a sense amplifier region and an input/output latch region.

Abstract: A dynamic random access memory (DRAM) includes a selection circuit for selecting the voltages used for aging. The selection circuit operates responsive to external control signals. When a source voltage (Vcc) is selected, the voltage (Vcc) is supplied to one electrode of a memory cell via a circuit 73 and a transmission gate while a ground potential (Vss) is supplied to the other electrode via a bit line and a transistor. Conversely, when the ground potential (Vss) is selected, an inverted voltage is applied across the two electrodes. In this manner, the insulating properties of an insulator interposed between the two electrodes can be checked more reliably during aging.

Abstract: Column repairing circuits 7a, 7b for repairing a DRAM in which there are defective memory cells in two columns are disclosed. The connection state of switching elements or circuits 51-5n, 61-6n, 71-7 (n+1), 81-8 (n+1) is determined as illustrated by appropriately disconnecting fuses in fuse links provided respectively in circuits 7a, 7b. Accordingly, column selecting lines Y2a and Y (n+1) b in memory array blocks 891a, 891b are not activated. The two repairing circuits 7a, 7b are provided spaced apart from each other on a semiconductor substrate, so that excessive concentration of fuse elements and switching elements or circuits is prevented.

Abstract: A semiconductor device having amplifying circuits provided near corresponding bonding pads receiving external signals, and positioned between the bonding pads and internal circuits to which such external signals are to be applied. The device includes a control signal generating circuit for the amplifying circuits which is not provided in conventional semiconductor devices. In response to external control signals, the control signal generating circuit generates internal control signals for controlling electric paths between a power supply and ground in the amplifying circuits. During the standby period of the semiconductor device, the paths between the power supply and ground are cut regardless of the potential of the corresponding bonding pads, preventing flow of a through current.

Abstract: A semiconductor memory device includes a first conductivity type well in a first conductivity type semiconductor substrate surrounded by a second conductivity type well, one of a memory cell and an external input circuit arranged on the first conductivity type well and the other disposed outside the second conductivity type well. A predetermined power supply voltage is applied to the second conductivity type well and the first conductivity type well is connected to ground. In the structure, charge carriers injected from the external input circuit are absorbed in the second conductivity type well. As a result, the charge carriers are prevented from reaching the memory cell and destroying data stored therein. Therefore, it is possible to miniaturize transistors and increase integration density of dynamic random access memory devices without degrading the source to drain dielectric strength.

Abstract: A DRAM includes a test mode controller generating a test mode designating signal designating a test mode at a fall of an external control signal RAS when the logical levels of external control signals CAS and WE are low, and a power-on reset circuit responsive to a power supply for generating a reset pulse for resetting main circuits for data reading and data writing. Each of the external control signals CAS and WE are supplied to the test mode controller and the main circuits through a buffer circuit. A first buffer circuit for supplying the external control signal RAS to the test mode controller is provided separately from a second buffer circuit for supplying the external control signal RAS to the main circuits. The second buffer circuit receives the output of the power-on reset circuit and the external control signal RAS to buffer the control signal RAS only when no reset pulse is generated.

Abstract: Disclosed are an RAS input circuit (100a) and a CAS input circuit (200a) applicable to a dynamic random access memory (DRAM). The threshold voltage V.sub.TRAS of the RAS input circuit and the threshold voltage V.sub.TCAS of the CAS input circuit are settled to satisfy the relation V.sub.TRAS >V.sub.TCAS. Therefore, a L level of an external RAS signal is more easily determined by a L level of an external CAS signal. As a result, the DRAM is prevented from erroneously starting its operation under a test mode without an external request.

Abstract: A dynamic random access memory (DRAM) includes a selection circuit for selecting the voltages used for aging. The switching circuit operates responsive to external control signals. When a source voltage (Vcc) is selected, the voltage (Vcc) is supplied to one electrode of a memory cell via a circuit 73 and a transmission gate while a ground potential (Vss) is supplied to the other electrode via a bit line and a transistor. Conversely, when the ground potential (Vss) is selected, an inverted voltage is applied across the two electrodes. In this manner, the insulating properties of an insulator interposed between the two electrodes can be checked more reliably during aging.

Abstract: A memory cell array is divided into four blocks. A sense amplifier and a restore circuit and provided in each of the blocks. The sense amplifier operates by a sense amplifier driving signal and the restore circuit operates by a restore circuit driving signal. A driving signal generating circuit generates two restore circuit driving signals at different timing. In order to generate the restore circuit driving signals, a block selecting signal, a block non-selecting signal, a sense amplifier driving signal and two dummy bit lines are used. Restoring operation in a block selected by the block selecting signal and restoring operation in a non-selected block are performed at different timing by the above described restore circuit driving signals.

Abstract: A semiconductor memory device includes a first conductivity type well in a first conductivity type semiconductor substrate surrounded by a second conductivity type well, one of a memory cell and an external input circuit arranged on the first conductivity type well and the other disposed outside the second conductivity type well. A predetermined power supply voltage is applied to the second conductivity type well and the first conductivity type well is connected to ground. In the structure, charge carriers injected from the external input circuit are absorbed in the second conductivity type well. As a result, the charge carriers are prevented from reaching the memory cell and destroying data stored therein. Therefore, it is possible to miniaturize transistors and increase integration density of dynamic random access memory devices without degrading the source to drain dielectric strength.