Patents by Inventor Makoto Suwada

Makoto Suwada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7103525
    Abstract: The high-frequency-corresponding simulation apparatus includes a control section that calculates a sum of the DC resistance value and skin resistance value of each of a plurality of elements corresponding to wiring patterns in accordance with circuit deign information, sorts resistance values corresponding to the elements by using a high-frequency element delay as a key when the total resistance value is equal to or larger than a first threshold value, integrates resistance values starting with a resistance value having the smallest high-frequency element delay, and which determines whether the result of the integration reaches a value immediately before a second threshold value whenever the integration is executed and a RLC-model analysis section.
    Type: Grant
    Filed: August 15, 2001
    Date of Patent: September 5, 2006
    Assignee: Fujitsu Limited
    Inventors: Makoto Suwada, Tatsuo Koizumi, Masaki Tosaka, Kazuhiko Tokuda, Jiro Yoneda
  • Patent number: 7065480
    Abstract: A noise countermeasure determination method includes the steps of calculating recommended circuit information considered to minimize a noise by use of at least one formula, based on input circuit information amounting to at least one net of a target circuit which is to be subjected to a noise analysis, and comparing the input circuit information and the recommended circuit information, and determining a differing portion of the recommended circuit information differing from the input circuit information, as noise countermeasures.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: June 20, 2006
    Assignee: Fujitsu Limited
    Inventors: Shogo Fujimori, Yasuhiro Yamashita, Ryoji Yamada, Masaki Tosaka, Kazuhiko Tokuda, Jiro Yoneda, Makoto Suwada, Tatsuo Koizumi
  • Patent number: 6925430
    Abstract: The apparatus includes the wiring-model generation section that generates a wiring model in accordance with high-frequency-circuit design information; the random-pattern analysis section that generates and analyzes a dummy random-pattern waveform for transmitting a wiring model in accordance with a command including the bit information of a random-pattern waveform and a differential waveform corresponding to the dummy random-pattern waveform; and the skew analysis section that skews a random-pattern waveform or differential waveform in accordance with a preset skew width.
    Type: Grant
    Filed: September 5, 2001
    Date of Patent: August 2, 2005
    Assignee: Fujitsu Limited
    Inventors: Makoto Suwada, Tatsuo Koizumi, Masaki Tosaka, Kazuhiko Tokuda, Jiro Yoneda
  • Patent number: 6662132
    Abstract: A noise analyzing method analyzes a crosstalk noise based on circuit data in which buses having the same signal transmitting direction and buses having opposite signal transmitting directions are distinguished from each other, by analyzing the crosstalk noise only for the same signal transmitting direction with respect to the buses having the same signal transmitting direction.
    Type: Grant
    Filed: December 11, 2000
    Date of Patent: December 9, 2003
    Assignee: Fujitsu Limited
    Inventors: Yasuhiro Yamashita, Shogo Fujimori, Ryoji Yamada, Kazuhiko Tokuda, Makoto Suwada, Masaki Tosaka, Jiro Yoneda, Yoshiyuki Iwakura, Kazunari Gotou
  • Publication number: 20020032556
    Abstract: The high-frequency-corresponding simulation apparatus includes a control section that calculates a sum of the DC resistance value and skin resistance value of each of a plurality of elements corresponding to wiring patterns in accordance with circuit deign information, sorts resistance values corresponding to the elements by using a high-frequency element delay as a key when the total resistance value is equal to or larger than a first threshold value, integrates resistance values starting with a resistance value having the smallest high-frequency element delay, and which determines whether the result of the integration reaches a value immediately before a second threshold value whenever the integration is executed and a RLC-model analysis section.
    Type: Application
    Filed: August 15, 2001
    Publication date: March 14, 2002
    Applicant: Fujitsu Limited
    Inventors: Makoto Suwada, Tatsuo Koizumi, Masaki Tosaka, Kazuhiko Tokuda, Jiro Yoneda
  • Publication number: 20020032555
    Abstract: The apparatus includes the wiring-model generation section that generates a wiring model in accordance with high-frequency-circuit design information; the random-pattern analysis section that generates and analyzes a dummy random-pattern waveform for transmitting a wiring model in accordance with a command including the bit information of a random-pattern waveform and a differential waveform corresponding to the dummy random-pattern waveform; and the skew analysis section that skews a random-pattern waveform or differential waveform in accordance with a preset skew width.
    Type: Application
    Filed: September 5, 2001
    Publication date: March 14, 2002
    Applicant: Fujitsu Limited
    Inventors: Makoto Suwada, Tatsuo Koizumi, Masaki Tosaka, Kazuhiko Tokuda, Jiro Yoneda
  • Publication number: 20020007253
    Abstract: A noise analyzing method analyzes a crosstalk noise based on circuit data in which buses having the same signal transmitting direction and buses having opposite signal transmitting directions are distinguished from each other, by analyzing the crosstalk noise only for the same signal transmitting direction with respect to the buses having the same signal transmitting direction.
    Type: Application
    Filed: December 11, 2000
    Publication date: January 17, 2002
    Inventors: Yasuhiro Yamashita, Shogo Fujimori, Ryoji Yamada, Kazuhiko Tokuda, Makoto Suwada, Masaki Tosaka, Jiro Yoneda, Yoshiyuki Iwakura, Kazunari Gotou
  • Publication number: 20010044709
    Abstract: A noise countermeasure determination method includes the step of obtaining an analyzing circuit judgement result by judging acceptability of the analyzing circuit based on a comparison of features of the analyzing circuit and transmission circuit topologies, and outputting an improvement proposal for making the analyzing circuit closer to one of basic types of the transmission circuit topologies depending on the analyzing circuit judgement result.
    Type: Application
    Filed: June 18, 2001
    Publication date: November 22, 2001
    Applicant: FUJITSU LIMITED
    Inventors: Shogo Fujimori, Yasuhiro Yamashita, Ryoji Yamada, Masaki Tosaka, Kazuhiko Tokuda, Jiro Yoneda, Makoto Suwada, Tatsuo Koizumi
  • Publication number: 20010041970
    Abstract: A noise countermeasure determination method includes the steps of calculating recommended circuit information considered to minimize a noise by use of at least one formula, based on input circuit information amounting to at least one net of a target circuit which is to be subjected to a noise analysis, and comparing the input circuit information and the recommended circuit information, and determining a differing portion of the recommended circuit information differing from the input circuit information, as noise countermeasures.
    Type: Application
    Filed: December 29, 2000
    Publication date: November 15, 2001
    Inventors: Shogo Fujimori, Yasuhiro Yamashita, Ryoji Yamada, Masaki Tosaka, Kazuhiko Tokuda, Jiro Yoneda, Makoto Suwada, Tatsuo Koizumi
  • Patent number: 5146188
    Abstract: A constant current circuit having an output current I.sub.2 which changes with the change of the power source voltage V.sub.cc, and an oscillating circuit whose oscillation frequency is made variable by the change of I.sub.2 in the constant current circuit. The constant current circuit comprises bipolar transistors coupled to form a differential amplifier, wherein one of the transistors is supplied with a reference voltage and another is supplied with a divided voltage of V.sub.cc, and a resistor connecting the emitters of the transistors is provided for controlling the slope of the V.sub.cc -I.sub.2 characteristic curve of the constant current circuit. The oscillating circuit comprises a capacitor charged with I.sub.2 and a switching circuit for discharging the capacitor when it is closed and a voltage detecting circuit operating to close or open the switching circuit according to the detection of the voltage at an end of the capacitor.
    Type: Grant
    Filed: September 25, 1991
    Date of Patent: September 8, 1992
    Assignee: Fujitsu Limited
    Inventors: Makoto Suwada, Shuichi Inoue, Yuzo Usui