Abstract: A programmable controller according to an embodiment includes a connection interface, a storage, and a controller. The connection interface can be connected with an external storage. The storage stores information for authentication. The controller accepts control for the programmable controller when the external storage is connected to the connection interface and the external storage is authenticated based on identification information stored in the external storage and the information for authentication.

Abstract: A programmable controller according to an embodiment includes a connection interface, a storage, and a controller. The connection interface can be connected with an external storage. The storage stores information for authentication. The controller accepts control for the programmable controller when the external storage is connected to the connection interface and the external storage is authenticated based on identification information stored in the external storage and the information for authentication.

Abstract: According to one embodiment, there is provided an output apparatus including a signal control unit configured to set a signal from a second output element in an OFF state at a timing earlier than a predetermined timing by the response time of a second load, and set signals from a first output element and the second output element in an ON state, and signals from a first interruption element and a second interruption element in an OFF state at a timing earlier than the predetermined timing by the response time of a first load. The output apparatus includes a diagnosis unit configured to diagnose, at the predetermined timing, whether the first and second interruption elements are in a normal state or a failure state, based on a signal from the first and second digital output circuits.

Abstract: A redundancy control system and method of transmitting computational data are provided, for detection of transmission errors and failure diagnosis, including generating first computational data and generating first generated data using a first generation algorithm for error detection; generating second computational data and generating second generated data using a second generation algorithm for error detection; comparing the first/second computational data; transmitting transmission data including coincident computational data and the first/second generated data; generating, in the receiving device, computational data and third/fourth generated data from preset first/second generation algorithms; and comparing the first/third generated data and the first/third generated data, and detecting the presence or absence of an error in the received computational data.

Abstract: An area of a memory has a diagnosis area and a non diagnosis area, with the diagnosis area divided into a plurality of Row areas which do not overlap each other, and each of the Row areas is divided into a plurality of Cell areas which do not overlap each other. A memory fault diagnostic method has a diagnostic step in a Row area to diagnose between Cell areas with respect to all the combinations of a set of Cell areas in the Row area, and a diagnostic step between Row areas to diagnose between Row areas with respect to all the combinations of a set of Row areas in the diagnosis area. A Row area size is determined to be a size in which a time of the diagnosis in a Row area becomes equal to a time of the diagnosis between Row areas.

Abstract: A clock diagnosis circuit includes: a delay circuit to delay the clock by a prescribed time which is not more than the clock pulse width; an integral multiplication delay circuit to delay a delayed clock outputted from the delay circuit by a prescribed number of cycles; a first exclusive OR circuit to encode the clock using the delayed clock; a second exclusive OR circuit to decode an output of the first exclusive OR circuit using an output of the integral multiplication delay circuit; and a comparison circuit to compare the clock with an output of the second exclusive OR circuit to thereby detect a malfunction of the clock.

Abstract: An area of a memory has a diagnosis area and a non diagnosis area, with the diagnosis area divided into a plurality of Row areas which do not overlap each other, and each of the Row areas is divided into a plurality of Cell areas which do not overlap each other. A memory fault diagnostic method has a diagnostic step in a Row area to diagnose between Cell areas with respect to all the combinations of a set of Cell areas in the Row area, and a diagnostic step between Row areas to diagnose between Row areas with respect to all the combinations of a set of Row areas in the diagnosis area. A Row area size is determined to be a size in which a time of the diagnosis in a Row area becomes equal to a time of the diagnosis between Row areas.

Abstract: A safety output includes an output controller to make an instruction to output normal output data and first self-diagnosis pattern data synchronously with a control cycle, a normal output unit to output the normal output data synchronously with the control cycle, a test pattern generating unit to encode the self-diagnosis pattern data into a pulse train signal having a pulse width not larger than a preset value and output the pulse train signal in accordance with a baseband transmission system, a combination output unit to combine the pulse train signal with the normal output signal and output the resultant signal, a reconfiguration unit to decode the inputted operation-terminal-portion output signal to reconfigure the operation-terminal-portion output signal as second self-diagnosis pattern data, and a comparator to compare the first self-diagnosis pattern data with the second self-diagnosis pattern data to judge the presence or absence of a difference.

Abstract: A safety input device includes an input controller to control transmission of an input signal to an arithmetic device, an output controller to instruct output of preset first self-diagnosis pattern data, a test pattern generating unit to encode the first self-diagnosis pattern data into a pulse train signal having a pulse width equal to or below a predetermined value and output the pulse train signal, a combination input unit to combine the pulse train signal with the input signal, an input interface unit, a pattern reconfiguration unit to decode an output signal from the combination input unit into second self-diagnosis pattern data, and a comparator to compare the first and second self-diagnosis pattern data to judge the presence or absence of a difference between the first and second self-diagnosis pattern data.

Abstract: A clock diagnosis circuit includes: a delay circuit to delay the clock by a prescribed time which is not more than the clock pulse width; an integral multiplication delay circuit to delay a delayed clock outputted from the delay circuit by a prescribed number of cycles; a first exclusive OR circuit to encode the clock using the delayed clock; a second exclusive OR circuit to decode an output of the first exclusive OR circuit using an output of the integral multiplication delay circuit; and a comparison circuit to compare the clock with an output of the second exclusive OR circuit to thereby detect a malfunction of the clock.

Abstract: A control device includes a diagnostic pulse signal generating section having an internal circuit that generates control data and generates diagnostic pulse data for diagnosing the operating terminal and diagnoses the function of the signal line and the operating terminal from the waveform of a feedback signal of the diagnostic pulse signal; a variable amplification circuit that multiplexes the diagnostic pulse signal on the control signal and sends the result to the operating terminal with a preset signal level; and a receiving circuit that receives the feedback signal and sends it to the internal circuit. The internal circuit comprises a correction pulse data generating section that corrects the diagnostic pulse data by correcting the rise time of the diagnostic pulse signal. Even if the length of the signal line is long, the diagnostic pulse signal reception can be achieved without expanding the pulse width of the diagnostic pulse signal.

Abstract: A processor includes a computation unit; a storage unit storing a program; and a data transmission circuit that transmits to an operation monitoring unit a signal corresponding to an instruction for reporting the execution stage of the program. The operation monitoring unit: includes a transition operation identification. circuit and a loop processing identification circuit. The transition operation identification circuit receives a start ID instruction with an attached ID that identifies a task; a termination ID instruction that identifies termination of task operation; and if the task is execution of loop processing, a loop instruction that reports the maximum value of the number of times of this loop processing. The transition operation identification circuit identifies success of the transition operations of the tasks of the program, based on the ID instructions. The loop processing identification circuit identifies abnormality of the number of times of loop processing.

Abstract: A method of transmitting computational data comprising: a step of generating first computational data and generating first generated data using a first generation algorithm for error detection on return; a step of generating second computational data and generating second generated data using a second generation algorithm for error detection; a step of mutually comparing the first/second computational data; a step of transmitting transmission data including coincident computational data and first/second generated data; in the receiving device, a step of generating computational data and third/fourth generated data from preset first/second generation algorithms; and a step of comparing the first/third generated data and the first/third generated data, and detecting error in the received computational data.

Abstract: First and second processing units execute the same control program to the same input data in parallel. An input/output unit generates the input data and receives one of two output data executed by the first and second processing units. A channel selection unit sends the input data to the first and second processing units and sends the one to the input/output unit by selecting the one from the two output data. In the first and second processing units, a control cycle synchronization unit generates a control cycle signal at a control cycle, a processor executes the control program, a data memory stores operation data including the input data, intermediate data being executed and output data executed by the processor. A diagnostics unit generates summary information by compressing the operation data and comparatively decides whether the summary information matches the other summary information of the other processing unit every control cycle.

Abstract: A safety input device includes an input controller to control transmission of an input signal to an arithmetic device synchronously with a control cycle set by the arithmetic device, an output controller to instruct output of preset first self-diagnosis pattern data, a test pattern generating unit to encode the first self-diagnosis pattern data into a pulse train signal having a pulse width equal to or below a predetermined value and output the pulse train signal in accordance with a baseband transmission system, a combination input unit to combine the pulse train signal with the input signal, an input interface unit, a pattern reconfiguration unit to decode an output signal from the combination input unit into second self-diagnosis pattern data, and a comparator to compare the first and second self-diagnosis pattern data to judge the presence or absence of a difference between the first and second self-diagnosis pattern data.

Abstract: A safety output includes an output controller to make an instruction to output normal output data and first self-diagnosis pattern data synchronously with a control cycle, a normal output unit to output the normal output data synchronously with the control cycle, a test pattern generating unit to encode the self-diagnosis pattern data into a pulse train signal having a pulse width not larger than a preset value and output the pulse train signal in accordance with a baseband transmission system, a combination output unit to combine the pulse train signal with the normal output signal and output the resultant signal, a reconfiguration unit to decode the inputted operation-terminal-portion output signal to reconfigure the operation-terminal-portion output signal as second self-diagnosis pattern data, and a comparator to compare the first self-diagnosis pattern data with the second self-diagnosis pattern data to judge the presence or absence of a difference.

Abstract: First and second processing units execute the same control program to the same input data in parallel. An input/output unit generates the input data and receives one of two output data executed by the first and second processing units. A channel selection unit sends the input data to the first and second processing units and sends the one to the input/output unit by selecting the one from the two output data. In the first and second processing units, a control cycle synchronization unit generates a control cycle signal at a control cycle, a processor executes the control program, a data memory stores operation data including the input data, intermediate data being executed and output data executed by the processor. A diagnostics unit generates summary information by compressing the operation data and comparatively decides whether the summary information matches the other summary information of the other processing unit every control cycle.

Abstract: An object is to provide a redundant supervisory control system and a redundancy switching method thereof. In the redundant supervisory control system, remote I/O apparatuses are less likely to be inaccessible, even in a case where failures occur in plural locations. Thus, the reliability of the system is enhanced. The redundant supervisory control system including a plurality of first loop interface units in each of a pair of controllers, second loop interface units, and communication cables each connecting the plurality of first and second loop interface units with one another in a circular loop. The redundant supervisory control system is configured by connecting the controllers and the remote I/O units to one another in a plurality of loop networks. In a case where abnormality in the loop networks is detected by use of received data in the networks, the first and second loop interface units that can perform normal reception are automatically selected.

Abstract: An object is to provide a redundant supervisory control system and a redundancy switching method thereof. In the redundant supervisory control system, remote I/O apparatuses are less likely to be inaccessible, even in a case where failures occur in plural locations. Thus, the reliability of the system is enhanced. The redundant supervisory control system including a plurality of first loop interface units in each of a pair of controllers, second loop interface units, and communication cables each connecting the plurality of first and second loop interface units with one another in a circular loop. The redundant supervisory control system is configured by connecting the controllers and the remote I/O units to one another in a plurality of loop networks. In a case where abnormality in the loop networks is detected by use of received data in the networks, the first and second loop interface units that can perform normal reception are automatically selected.

Abstract: A multiple-input digital filter capable of filtering a plurality of digital input signals with a single filtering device first latches the input signals and then sequentially selects each of the digital input signals for output to a counter circuit. The counter circuit, which is preset by the previous count value for the corresponding digital input signal, counts up or down depending on the digital input signal. When the count value reaches its maximum, a decision value signal is set for the corresponding digital input signal until the count value for that digital input signal returns to the minimum value. The count values are stored in a shift register which supplies the count value corresponding to the digital input signal as a preset value to the counter. A second shift register stores the decision values corresponding to each of the digital input signals which are then latched for simultaneous output.