Patents by Inventor Makoto Tsutsue
Makoto Tsutsue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11749554Abstract: A multi-wafer deposition tool includes a vacuum enclosure including a platen laterally surrounding multiple wafer stages, a spindle-blade assembly including a spindle and multiple transfer blades attached to the spindle, and a controller configured to transfer wafers between the multiple wafer stages through rotation of the multiple transfer blades around a rotation axis pasting through the spindle. A chamber clean process may be performed while the transfer blades of the spindle-blade assembly are positioned over the multiple wafer stages. Alternatively or additionally, a deposition cycle may be performed while the transfer blades of the spindle-blade assembly are positioned between neighboring pairs of the wafer stages and while a purge gas that flows out of purge gas openings into spaces between the wafer stages.Type: GrantFiled: November 5, 2020Date of Patent: September 5, 2023Assignee: SANDISK TECHNOLOGIES LLCInventors: Makoto Tsutsue, Shunsuke Takuma
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Patent number: 11702750Abstract: A patterned backside stress compensation film having different stress in different sectors is formed on a backside of a substrate to reduce combination warpage of the substrate. The film can be formed by employing a radio frequency electrode assembly including plurality of conductive plates that are biased with different RF power and cause local variations in the plasma employed to deposit the backside film. Alternatively, the film may be deposited with uniform stress, and some of its sectors are irradiated with ultraviolet radiation to change the stress of these irradiated sectors. Yet alternatively, multiple backside deposition processes may be sequentially employed to deposit different backside films to provide a composite backside film having different stresses in different sectors.Type: GrantFiled: June 10, 2020Date of Patent: July 18, 2023Assignee: SANDISK TECHNOLOGIES LLCInventors: Seiji Shimabukuro, Makoto Tsutsue
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Patent number: 11473199Abstract: A patterned backside stress compensation film having different stress in different sectors is formed on a backside of a substrate to reduce combination warpage of the substrate. The film can be formed by employing a radio frequency electrode assembly including plurality of conductive plates that are biased with different RF power and cause local variations in the plasma employed to deposit the backside film. Alternatively, the film may be deposited with uniform stress, and some of its sectors are irradiated with ultraviolet radiation to change the stress of these irradiated sectors. Yet alternatively, multiple backside deposition processes may be sequentially employed to deposit different backside films to provide a composite backside film having different stresses in different sectors.Type: GrantFiled: June 10, 2020Date of Patent: October 18, 2022Assignee: SANDISK TECHNOLOGIES LLCInventors: Seiji Shimabukuro, Makoto Tsutsue
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Publication number: 20220139758Abstract: A multi-wafer deposition tool includes a vacuum enclosure including a platen laterally surrounding multiple wafer stages, a spindle-blade assembly including a spindle and multiple transfer blades attached to the spindle, and a controller configured to transfer wafers between the multiple wafer stages through rotation of the multiple transfer blades around a rotation axis pasting through the spindle. A chamber clean process may be performed while the transfer blades of the spindle-blade assembly are positioned over the multiple wafer stages. Alternatively or additionally, a deposition cycle may be performed while the transfer blades of the spindle-blade assembly are positioned between neighboring pairs of the wafer stages and while a purge gas that flows out of purge gas openings into spaces between the wafer stages.Type: ApplicationFiled: November 5, 2020Publication date: May 5, 2022Inventors: Makoto TSUTSUE, Shunsuke TAKUMA
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Publication number: 20210388502Abstract: A patterned backside stress compensation film having different stress in different sectors is formed on a backside of a substrate to reduce combination warpage of the substrate. The film can be formed by employing a radio frequency electrode assembly including plurality of conductive plates that are biased with different RF power and cause local variations in the plasma employed to deposit the backside film. Alternatively, the film may be deposited with uniform stress, and some of its sectors are irradiated with ultraviolet radiation to change the stress of these irradiated sectors. Yet alternatively, multiple backside deposition processes may be sequentially employed to deposit different backside films to provide a composite backside film having different stresses in different sectors.Type: ApplicationFiled: June 10, 2020Publication date: December 16, 2021Inventors: Seiji SHIMABUKURO, Makoto TSUTSUE
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Publication number: 20210388500Abstract: A patterned backside stress compensation film having different stress in different sectors is formed on a backside of a substrate to reduce combination warpage of the substrate. The film can be formed by employing a radio frequency electrode assembly including plurality of conductive plates that are biased with different RF power and cause local variations in the plasma employed to deposit the backside film. Alternatively, the film may be deposited with uniform stress, and some of its sectors are irradiated with ultraviolet radiation to change the stress of these irradiated sectors. Yet alternatively, multiple backside deposition processes may be sequentially employed to deposit different backside films to provide a composite backside film having different stresses in different sectors.Type: ApplicationFiled: June 10, 2020Publication date: December 16, 2021Inventors: Seiji SHIMABUKURO, Makoto TSUTSUE
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Patent number: 9673154Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.Type: GrantFiled: May 5, 2016Date of Patent: June 6, 2017Assignee: PANASONIC CORPORATIONInventors: Makoto Tsutsue, Masaki Utsumi
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Publication number: 20160247771Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.Type: ApplicationFiled: May 5, 2016Publication date: August 25, 2016Inventors: Makoto TSUTSUE, Masaki UTSUMI
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Patent number: 9082779Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.Type: GrantFiled: March 31, 2014Date of Patent: July 14, 2015Assignee: PANASONIC CORPORATIONInventors: Makoto Tsutsue, Masaki Utsumi
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Publication number: 20150194391Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.Type: ApplicationFiled: March 19, 2015Publication date: July 9, 2015Inventors: Makoto TSUTSUE, Masaki UTSUMI
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Publication number: 20140210056Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.Type: ApplicationFiled: March 31, 2014Publication date: July 31, 2014Applicant: Panasonic CorporationInventors: Makoto TSUTSUE, Masaki UTSUMI
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Patent number: 8710595Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.Type: GrantFiled: July 12, 2013Date of Patent: April 29, 2014Assignee: Panasonic CorporationInventors: Makoto Tsutsue, Masaki Utsumi
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Patent number: 8618618Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.Type: GrantFiled: July 17, 2012Date of Patent: December 31, 2013Assignee: Panasonic CorporationInventors: Makoto Tsutsue, Masaki Utsumi
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Publication number: 20130299948Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.Type: ApplicationFiled: July 12, 2013Publication date: November 14, 2013Inventors: Makoto TSUTSUE, Masaki UTSUMI
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Patent number: 8564136Abstract: A semiconductor device includes an interlayer dielectric with a single-layer structure having a plurality of pores. The porosity of the interlayer dielectric per unit volume varies in a thickness direction.Type: GrantFiled: March 2, 2011Date of Patent: October 22, 2013Assignee: Panasonic CorporationInventor: Makoto Tsutsue
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Patent number: 8508002Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.Type: GrantFiled: July 17, 2012Date of Patent: August 13, 2013Assignee: Panasonic CorporationInventors: Makoto Tsutsue, Masaki Utsumi
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Publication number: 20120280401Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.Type: ApplicationFiled: July 17, 2012Publication date: November 8, 2012Applicant: Panasonic CorporationInventors: Makoto TSUTSUE, Masaki UTSUMI
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Patent number: 8247876Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.Type: GrantFiled: June 28, 2011Date of Patent: August 21, 2012Assignee: Panasonic CorporationInventors: Makoto Tsutsue, Masaki Utsumi
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Publication number: 20110254136Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.Type: ApplicationFiled: June 28, 2011Publication date: October 20, 2011Applicant: Panaconic CorporationInventors: Makoto TSUTSUE, Masaki Utsumi
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Patent number: 8035197Abstract: An electronic device has an element formed in the chip region of a substrate, a plurality of interlayer insulating films formed on the substrate, a wire formed in the interlayer insulating films in the chip region, and a plug formed in the interlayer insulating films in the chip region and connecting to the wire. A seal ring extending through the plurality of interlayer insulating films and continuously surrounding the chip region is formed in the peripheral portion of the chip region. A stress absorbing wall extending through the plurality of interlayer insulating films and discretely surrounding the seal ring is formed outside the seal ring.Type: GrantFiled: July 28, 2010Date of Patent: October 11, 2011Assignee: Panasonic CorporationInventor: Makoto Tsutsue