Patents by Inventor Makoto Tsutsue
Makoto Tsutsue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11749554Abstract: A multi-wafer deposition tool includes a vacuum enclosure including a platen laterally surrounding multiple wafer stages, a spindle-blade assembly including a spindle and multiple transfer blades attached to the spindle, and a controller configured to transfer wafers between the multiple wafer stages through rotation of the multiple transfer blades around a rotation axis pasting through the spindle. A chamber clean process may be performed while the transfer blades of the spindle-blade assembly are positioned over the multiple wafer stages. Alternatively or additionally, a deposition cycle may be performed while the transfer blades of the spindle-blade assembly are positioned between neighboring pairs of the wafer stages and while a purge gas that flows out of purge gas openings into spaces between the wafer stages.Type: GrantFiled: November 5, 2020Date of Patent: September 5, 2023Assignee: SANDISK TECHNOLOGIES LLCInventors: Makoto Tsutsue, Shunsuke Takuma
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Patent number: 11702750Abstract: A patterned backside stress compensation film having different stress in different sectors is formed on a backside of a substrate to reduce combination warpage of the substrate. The film can be formed by employing a radio frequency electrode assembly including plurality of conductive plates that are biased with different RF power and cause local variations in the plasma employed to deposit the backside film. Alternatively, the film may be deposited with uniform stress, and some of its sectors are irradiated with ultraviolet radiation to change the stress of these irradiated sectors. Yet alternatively, multiple backside deposition processes may be sequentially employed to deposit different backside films to provide a composite backside film having different stresses in different sectors.Type: GrantFiled: June 10, 2020Date of Patent: July 18, 2023Assignee: SANDISK TECHNOLOGIES LLCInventors: Seiji Shimabukuro, Makoto Tsutsue
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Patent number: 11473199Abstract: A patterned backside stress compensation film having different stress in different sectors is formed on a backside of a substrate to reduce combination warpage of the substrate. The film can be formed by employing a radio frequency electrode assembly including plurality of conductive plates that are biased with different RF power and cause local variations in the plasma employed to deposit the backside film. Alternatively, the film may be deposited with uniform stress, and some of its sectors are irradiated with ultraviolet radiation to change the stress of these irradiated sectors. Yet alternatively, multiple backside deposition processes may be sequentially employed to deposit different backside films to provide a composite backside film having different stresses in different sectors.Type: GrantFiled: June 10, 2020Date of Patent: October 18, 2022Assignee: SANDISK TECHNOLOGIES LLCInventors: Seiji Shimabukuro, Makoto Tsutsue
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Patent number: 9673154Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.Type: GrantFiled: May 5, 2016Date of Patent: June 6, 2017Assignee: PANASONIC CORPORATIONInventors: Makoto Tsutsue, Masaki Utsumi
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Patent number: 9082779Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.Type: GrantFiled: March 31, 2014Date of Patent: July 14, 2015Assignee: PANASONIC CORPORATIONInventors: Makoto Tsutsue, Masaki Utsumi
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Patent number: 8710595Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.Type: GrantFiled: July 12, 2013Date of Patent: April 29, 2014Assignee: Panasonic CorporationInventors: Makoto Tsutsue, Masaki Utsumi
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Patent number: 8618618Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.Type: GrantFiled: July 17, 2012Date of Patent: December 31, 2013Assignee: Panasonic CorporationInventors: Makoto Tsutsue, Masaki Utsumi
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Patent number: 8564136Abstract: A semiconductor device includes an interlayer dielectric with a single-layer structure having a plurality of pores. The porosity of the interlayer dielectric per unit volume varies in a thickness direction.Type: GrantFiled: March 2, 2011Date of Patent: October 22, 2013Assignee: Panasonic CorporationInventor: Makoto Tsutsue
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Patent number: 8508002Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.Type: GrantFiled: July 17, 2012Date of Patent: August 13, 2013Assignee: Panasonic CorporationInventors: Makoto Tsutsue, Masaki Utsumi
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Patent number: 8247876Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.Type: GrantFiled: June 28, 2011Date of Patent: August 21, 2012Assignee: Panasonic CorporationInventors: Makoto Tsutsue, Masaki Utsumi
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Patent number: 8035197Abstract: An electronic device has an element formed in the chip region of a substrate, a plurality of interlayer insulating films formed on the substrate, a wire formed in the interlayer insulating films in the chip region, and a plug formed in the interlayer insulating films in the chip region and connecting to the wire. A seal ring extending through the plurality of interlayer insulating films and continuously surrounding the chip region is formed in the peripheral portion of the chip region. A stress absorbing wall extending through the plurality of interlayer insulating films and discretely surrounding the seal ring is formed outside the seal ring.Type: GrantFiled: July 28, 2010Date of Patent: October 11, 2011Assignee: Panasonic CorporationInventor: Makoto Tsutsue
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Patent number: 7994589Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.Type: GrantFiled: August 18, 2010Date of Patent: August 9, 2011Assignee: Panasonic CorporationInventors: Makoto Tsutsue, Masaki Utsumi
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Patent number: 7989334Abstract: In a method of manufacturing a semiconductor device which method is made up of a process of forming a wiring groove using a hard mask, a metal hard mask 107 is used to form a wiring groove 111, allowing the shape of the wiring groove 111 to be stabilized. Furthermore, a part or all of the metal hard mask 107 is removed before the formation of TaN and Cu layers in the wiring groove 111. This enables a reduction in possible damage, which may increase the dielectric constant of the surface of low-dielectric-constant film, and thus in possible inter-wire leakage current. As a result, a reliable semiconductor device can be provided.Type: GrantFiled: March 6, 2009Date of Patent: August 2, 2011Assignee: Panasonic CorporationInventor: Makoto Tsutsue
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Patent number: 7985675Abstract: A semiconductor device includes: a semiconductor substrate; a first insulating film (third insulating film 24) formed on the semiconductor substrate, having a first trench (second interconnect trench 28), and having a composition ratio varying along the depth from an upper face of the first insulating film; and a first metal interconnect (second metal interconnect 25) filling the first trench (second interconnect trench 28). The mechanical strength in an upper portion of the first insulating film (third insulating film 24) is higher than that in the other portion of the insulating film (third insulating film 24).Type: GrantFiled: October 15, 2008Date of Patent: July 26, 2011Assignee: Panasonic CorporationInventors: Kotaro Nomura, Makoto Tsutsue
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Patent number: 7948039Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.Type: GrantFiled: November 4, 2008Date of Patent: May 24, 2011Assignee: Panasonic CorporationInventors: Makoto Tsutsue, Masaki Utsumi
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Publication number: 20110081776Abstract: A first insulating film is formed on or above a substrate, and a first conductor is formed in an upper portion of the formed first insulating film. Then, a second insulating film is formed on the first insulating film so as to cover the first conductor. Then, a film quality alteration process is performed for the second insulating film. Moreover, a third insulating film is formed on the second insulating film, and a curing process is performed for the formed third insulating film.Type: ApplicationFiled: June 24, 2010Publication date: April 7, 2011Inventors: Kotaro NOMURA, Makoto Tsutsue
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Publication number: 20100314720Abstract: An electronic device has an element formed in the chip region of a substrate, a plurality of interlayer insulating films formed on the substrate, a wire formed in the interlayer insulating films in the chip region, and a plug formed in the interlayer insulating films in the chip region and connecting to the wire. A seal ring extending through the plurality of interlayer insulating films and continuously surrounding the chip region is formed in the peripheral portion of the chip region. A stress absorbing wall extending through the plurality of interlayer insulating films and discretely surrounding the seal ring is formed outside the seal ring.Type: ApplicationFiled: July 28, 2010Publication date: December 16, 2010Applicant: PANASONIC CORPORATIONInventor: Makoto Tsutsue
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Patent number: 7795705Abstract: A semiconductor device includes an element formed on a substrate, at least one insulating film formed on the substrate, and a seal ring formed in the insulating film so as to surround a region where the element is formed and to extend through the insulating film. The semiconductor device further includes a void region including a void and formed in the insulating film in a region located outside the seal ring when viewed from the element.Type: GrantFiled: September 15, 2008Date of Patent: September 14, 2010Assignee: Panasonic CorporationInventor: Makoto Tsutsue
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Publication number: 20090181536Abstract: In a method of manufacturing a semiconductor device which method is made up of a process of forming a wiring groove using a hard mask, a metal hard mask 107 is used to form a wiring groove 111, allowing the shape of the wiring groove 111 to be stabilized. Furthermore, a part or all of the metal hard mask 107 is removed before the formation of TaN and Cu layers in the wiring groove 111. This enables a reduction in possible damage, which may increase the dielectric constant of the surface of low-dielectric-constant film, and thus in possible inter-wire leakage current. As a result, a reliable semiconductor device can be provided.Type: ApplicationFiled: March 6, 2009Publication date: July 16, 2009Applicant: PANASONIC CORPORATIONInventor: Makoto Tsutsue
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Publication number: 20090121359Abstract: A semiconductor device includes: a semiconductor substrate; a first insulating film (third insulating film 24) formed on the semiconductor substrate, having a first trench (second interconnect trench 28), and having a composition ratio varying along the depth from an upper face of the first insulating film; and a first metal interconnect (second metal interconnect 25) filling the first trench (second interconnect trench 28). The mechanical strength in an upper portion of the first insulating film (third insulating film 24) is higher than that in the other portion of the insulating film (third insulating film 24).Type: ApplicationFiled: October 15, 2008Publication date: May 14, 2009Inventors: Kotaro Nomura, Makoto Tsutsue