Patents by Inventor Makoto Wada

Makoto Wada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8022461
    Abstract: A semiconductor device includes a plurality of bit lines repeatedly arranged with a same line width and pitch in a memory device region; a plurality of shunt lines arranged in a same layer as that of the plurality of bit lines, in parallel therewith, and with the same line width and pitch as those of the plurality of bit lines in the memory device region; and an upper-layer contact plug arranged from an upper-layer side so as to be connected to the plurality of shunt lines by extending over two or more shunt lines.
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: September 20, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Wada, Akihiro Kajita, Kazuyuki Higashi
  • Publication number: 20110189849
    Abstract: A method of manufacturing a semiconductor device, including forming an opening in an interlevel insulating film disposed on a semiconductor substrate, forming an auxiliary film containing a predetermined metal element, to cover an inner surface of the opening, forming a main film to fill the opening after forming the auxiliary film, the main film containing, as a main component, Cu used as a material of an interconnection main layer, and performing a heat treatment before or after forming the main film, thereby diffusing the predetermined metal element of the auxiliary film onto a surface of the interlevel insulating film facing the auxiliary film, so as to form a barrier film on the interlevel insulating film within the opening, the barrier film containing, as a main component, a compound of the predetermined metal element with a component element of the interlevel insulating film.
    Type: Application
    Filed: April 14, 2011
    Publication date: August 4, 2011
    Applicant: SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER
    Inventors: Junichi KOIKE, Makoto Wada, Shingo Takahashi, Noriyoshi Shimizu, Hideki Shibata, Satoshi Nishikawa, Takamasa Usui, Hayato Nasu, Masaki Yoshimaru
  • Patent number: 7989880
    Abstract: A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The wiring comprises a plurality of second conductive layers extending upwardly from an upper surface of the first conductive layers comprising the stepped portion. The plurality of second conductive layers are formed such that upper ends thereof are aligned with a surface parallel to the substrate, and such that a diameter thereof decreases from the upper end thereof to a lower end thereof. The plurality of second conductive layers are formed such that the greater a length thereof in the perpendicular direction, the larger a diameter of the upper end thereof.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: August 2, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Wada, Kazuyuki Higashi, Naofumi Nakamura, Tsuneo Uenaka
  • Patent number: 7943517
    Abstract: A method of manufacturing a semiconductor device, including forming an opening in an interlevel insulating film disposed on a semiconductor substrate, forming an auxiliary film containing a predetermined metal element, to cover an inner surface of the opening, forming a main film to fill the opening after forming the auxiliary film, the main film containing, as a main component, Cu used as a material of an interconnection main layer, and performing a heat treatment before or after forming the main film, thereby diffusing the predetermined metal element of the auxiliary film onto a surface of the interlevel insulating film facing the auxiliary film, so as to form a barrier film on the interlevel insulating film within the opening, the barrier film containing, as a main component, a compound of the predetermined metal element with a component element of the interlevel insulating film.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: May 17, 2011
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Junichi Koike, Makoto Wada, Shingo Takahashi, Noriyoshi Shimizu, Hideki Shibata, Satoshi Nishikawa, Takamasa Usui, Hayato Nasu, Masaki Yoshimaru
  • Publication number: 20110101528
    Abstract: A semiconductor device according to one embodiment includes: a substrate; a wiring provided above the substrate and including a graphene nanoribbon layer comprising a plurality of laminated graphene nanoribbon sheets; and a wiring connecting member penetrating at least one of the plurality of graphene nanoribbon sheets for connecting the wiring and a conductive member above or below the wiring.
    Type: Application
    Filed: January 29, 2010
    Publication date: May 5, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yousuke Akimoto, Makoto Wada
  • Publication number: 20110057322
    Abstract: According to one embodiment, a carbon nanotube interconnect includes a first interconnection layer, an interlayer dielectric film, a second interconnection layer, a contact hole, a plurality of carbon nanotubes and a film. The interlayer dielectric film is formed on the first interconnection layer. The second interconnection layer is formed on the interlayer dielectric film. The contact hole is formed in the interlayer dielectric film between the first interconnection layer and the second interconnection layer. The carbon nanotubes are formed in the contact hole. The carbon nanotubes have a first end connected to the first interconnection layer and a second end connected to the second interconnection layer. The film is formed between the interlayer dielectric film and the second interconnection layer. The film has a portion filled between the second ends of the carbon nanotubes.
    Type: Application
    Filed: September 7, 2010
    Publication date: March 10, 2011
    Inventors: Noriaki MATSUNAGA, Makoto Wada, Yosuke Akimoto, Tadashi Sakai, Naoshi Sakuma, Masayuki Katagiri, Yuichi Yamazaki
  • Patent number: 7875976
    Abstract: In one aspect of the present invention, a semiconductor device may include a semiconductor substrate, a silicide layer provided on the semiconductor substrate, a dielectric layer provided on the semiconductor substrate, a contact layer provided on the silicide layer, a metal layer provided in the dielectric layer and electrically connected to the silicide layer via the contact layer, a diffusion barrier layer provided between the dielectric layer and the metal layer, wherein the contact layer includes a first metal element provided in the metal layer, a second metal element provided in the diffusion barrier layer and at least one of a third metal provided in the silicide layer and Si element.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: January 25, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Wada, Takamasa Usui, Kazuya Ohuchi
  • Publication number: 20110006425
    Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate; an insulating film provided on the semiconductor substrate and containing a wiring trench; a first catalyst layer provided directly or via another member on side and bottom surfaces of the wiring trench; and a first graphene layer provided in the wiring trench so as to be along the side and bottom surface of the wiring trench, the first graphene layer being provided on the first catalyst layer so as to be in contact with the first catalyst layer.
    Type: Application
    Filed: March 18, 2010
    Publication date: January 13, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Makoto Wada, Noriaki Matsunaga, Yosuke Akimoto
  • Publication number: 20100213526
    Abstract: A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The wiring comprises a plurality of second conductive layers extending upwardly from an upper surface of the first conductive layers comprising the stepped portion. The plurality of second conductive layers are formed such that upper ends thereof are aligned with a surface parallel to the substrate, and such that a diameter thereof decreases from the upper end thereof to a lower end thereof. The plurality of second conductive layers are formed such that the greater a length thereof in the perpendicular direction, the larger a diameter of the upper end thereof.
    Type: Application
    Filed: November 10, 2009
    Publication date: August 26, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Makoto WADA, Kazuyuki HIGASHI, Naofumi NAKAMURA, Tsuneo UENAKA
  • Publication number: 20100181673
    Abstract: A method for fabricating a semiconductor device, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a first film containing a metal whose energy for forming silicide thereof is lower than that of Cu silicide inside the opening; forming a second film that is conductive and contains copper (Cu) in the opening in which the first film containing the metal is formed; and forming a compound film containing Cu and silicon (Si) selectively on the second film in an atmosphere in which a temperature of the substrate is below 300° C.
    Type: Application
    Filed: January 5, 2010
    Publication date: July 22, 2010
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yumi HAYASHI, Atsuko Sakata, Kei Watanabe, Noriaki Matsunaga, Shinichi Nakao, Makoto Wada, Hiroshi Toyoda
  • Publication number: 20100145515
    Abstract: A robot system includes a robot arm driven by a motor, a collision detector that detects a collision between the robot arm and an obstacle, which is provided on the robot arm, and a stopping method selector that controls the robot arm by selecting any one of all stopping methods on the basis of the information obtained by the collision detector, thereby selecting a stopping method in accordance with the status of the collision.
    Type: Application
    Filed: August 10, 2009
    Publication date: June 10, 2010
    Applicant: KABUSHIKI KAISHA YASKAWA DENKI
    Inventors: Mitsuaki NAKANISHI, Makoto WADA
  • Publication number: 20090317691
    Abstract: An ejector for a fuel cell system of the present invention includes a nozzle having a nozzle hole for discharging hydrogen supplied via an inlet port of an ejector body, a diffuser for mixing hydrogen discharged from the nozzle hole and hydrogen off-gas discharged and returned via a circulation passage from a fuel cell, a needle displacing in the axial direction by a driving force of a solenoid, and a bearing member held in a hollow portion of the nozzle, and having a through hole that movably supports the needle in the axial direction.
    Type: Application
    Filed: June 12, 2009
    Publication date: December 24, 2009
    Applicant: Keihin Corporation
    Inventors: Kouichi Yamada, Kazunori Fukuma, Makoto Wada
  • Publication number: 20090289281
    Abstract: A semiconductor device includes a plurality of bit lines repeatedly arranged with a same line width and pitch in a memory device region; a plurality of shunt lines arranged in a same layer as that of the plurality of bit lines, in parallel therewith, and with the same line width and pitch as those of the plurality of bit lines in the memory device region; and an upper-layer contact plug arranged from an upper-layer side so as to be connected to the plurality of shunt lines by extending over two or more shunt lines.
    Type: Application
    Filed: May 19, 2009
    Publication date: November 26, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Makoto WADA, Akihiro KAJITA, Kazuyuki HIGASHI
  • Publication number: 20090206491
    Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a connecting member formed above the semiconductor substrate configured to electrically connect upper and lower conductive members; a first insulating film formed in the same layer as the connecting member; a wiring formed on the connecting member, the wiring including a first region and a second region, the first region contacting with a portion of an upper surface of the connecting member, and the second region located on the first region and having a width greater than that of the first region; and a second insulating film formed on the first insulating film so as to contact with at least a portion of the first region of the wiring and with a bottom surface of the second region.
    Type: Application
    Filed: January 29, 2009
    Publication date: August 20, 2009
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Makoto Wada, Akihiro Kajita, Kazuyuki Higashi
  • Publication number: 20090191712
    Abstract: In one aspect of the present invention, a method of manufacturing a semiconductor device may include forming a first film on an amorphous silicon layer to be patterned, the first film and the amorphous film having a line-and-space ratio of approximately 3:1, sliming down, after processing the first film, a line portion of the pattern from both longitudinal sides of the line portion until the width of the line portion is reduced to approximately one third, reforming a part of the amorphous silicon layer where the first film is not provided such that reformed part has different etching ratio, and removing the first film and the amorphous silicon layer other than reformed part.
    Type: Application
    Filed: September 10, 2008
    Publication date: July 30, 2009
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazuyuki HIGASHI, Takuji Kuniya, Makoto Wada, Akihiro Kajita
  • Publication number: 20090085214
    Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a first conductive member formed on the semiconductor substrate; a first insulating film formed on the same layer as the first conductive member; a second conductive member formed so as to contact with a portion of an upper surface of the first conductive member, a second insulating film formed on the first insulating film so as to contact with a portion of the upper surface of the first conductive member, and including at least one type of element among elements contained in the first insulating film except Si; and an etching stopper film formed on the second insulating film so as to contact with a portion of a side surface of the second conductive member, and having an upper edge located below the upper surface of the second conductive member.
    Type: Application
    Filed: September 26, 2008
    Publication date: April 2, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Makoto WADA, Kazuyuki Higashi
  • Publication number: 20080088021
    Abstract: In one aspect of the present invention, a semiconductor device may include a semiconductor substrate, a silicide layer provided on the semiconductor substrate, a dielectric layer provided on the semiconductor substrate, a contact layer provided on the silicide layer, a metal layer provided in the dielectric layer and electrically connected to the silicide layer via the contact layer, a diffusion barrier layer provided between the dielectric layer and the metal layer, wherein the contact layer includes a first metal element provided in the metal layer, a second metal element provided in the diffusion barrier layer and at least one of a third metal provided in the silicide layer and Si element.
    Type: Application
    Filed: October 5, 2007
    Publication date: April 17, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Makoto WADA, Takamasa Usui, Kazuya Ohuchi
  • Publication number: 20080057704
    Abstract: A method of manufacturing a semiconductor device, including forming an opening in an interlevel insulating film disposed on a semiconductor substrate, forming an auxiliary film containing a predetermined metal element, to cover an inner surface of the opening, forming a main film to fill the opening after forming the auxiliary film, the main film containing, as a main component, Cu used as a material of an interconnection main layer, and performing a heat treatment before or after forming the main film, thereby diffusing the predetermined metal element of the auxiliary film onto a surface of the interlevel insulating film facing the auxiliary film, so as to form a barrier film on the interlevel insulating film within the opening, the barrier film containing, as a main component, a compound of the predetermined metal element with a component element of the interlevel insulating film.
    Type: Application
    Filed: October 23, 2007
    Publication date: March 6, 2008
    Applicant: SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER
    Inventors: Junichi Koike, Makoto Wada, Shingo Takahashi, Noriyoshi Shimizu, Hideki Shibata, Satoshi Nishikawa, Takamasa Usui, Hayato Nasu, Masaki Yoshimaru
  • Patent number: 7304384
    Abstract: A semiconductor device includes an interlevel insulating film disposed on a semiconductor substrate and having an opening formed therein. An interconnection main layer, which contains Cu as a main component, is embedded in the opening. A barrier film is interposed between the interlevel insulating film and the interconnection main layer within the opening. The barrier film contains, as a main component, a compound of a predetermined metal element with a component element of the interlevel insulating film.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: December 4, 2007
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Junichi Koike, Makoto Wada, Shingo Takahashi, Noriyoshi Shimizu, Hideki Shibata, Satoshi Nishikawa, Takamasa Usui, Hayato Nasu, Masaki Yoshimaru
  • Publication number: 20070044312
    Abstract: The invention relates to a bearing sleeve fixing mechanism adapted for a fan device to cool a heat generating component like MPU incorporated into a personal computer or a heat sink thermally connected to the heat generating component, a method of manufacturing the bearing sleeve fixing mechanism, and a fan device having the bearing sleeve fixing mechanism. The bearing sleeve fixing mechanism comprises: a shaft; a bearing sleeve, into which one end portion of the shaft is inserted, for pivotally supporting the shaft; a housing for accommodating the bearing sleeve; and a fixing ring press-fitted into the housing so that the bearing sleeve can be interposed between the fixing ring and a receiving mount provided in the housing, wherein the fixing ring fixes the bearing sleeve by giving a plastic deformation to the housing so that a recess portion can be formed in the housing.
    Type: Application
    Filed: August 25, 2006
    Publication date: March 1, 2007
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Masahiko Hirata, Yasushi Ayabe, Makoto Wada